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31. 发明公开

EP2732967A1 LAYERED BODY AND MANUFACTURING METHOD FOR LAYERED BODY 审中-公开
标题翻译： SCHICHTKÖRPERUND HERSTELLUNGSVERFAHRENFÜRSCHICHTKÖRPER
公开(公告)号：EP2732967A1
公开(公告)日：2014-05-21
申请号：EP12810573.1
申请日：2012-07-11
申请人： NHK Spring Co., Ltd.
发明人： YAMAUCHI, Yuichiro , HIRANO, Satoshi , SAITO, Shinji , HANAMACHI, Toshihiko
IPC分类号： B32B15/04 , B05D1/12 , C23C24/04
CPC分类号： B32B15/04 , B05D1/12 , C04B37/026 , C04B2237/121 , C04B2237/126 , C04B2237/128 , C04B2237/34 , C04B2237/341 , C04B2237/343 , C04B2237/346 , C04B2237/348 , C04B2237/366 , C04B2237/368 , C04B2237/402 , C04B2237/706 , C23C24/04 , C23C28/02 , C23C28/30 , H01L21/4846 , H01L23/3735 , H01L23/498 , H01L2224/291 , H01L2224/32225 , H01L2224/83447 , H01L2924/1305 , H01L2924/13055 , H05K1/0306 , H05K3/14 , H05K3/38 , H05K2201/0341 , H05K2201/0355 , H05K2203/1344 , Y10T428/12056 , H01L2924/014 , H01L2924/00
摘要： When a laminated body having a metal film formed on a ceramic base member is manufactured by using a cold spraying method, a laminated body having a high adhesion strength between a ceramic and the metal film and a method of manufacturing such a laminated body are provided. The laminated body includes a ceramic base member 10 having an insulating property, an intermediate layer 50 including metal or alloy as a main component formed on a surface of the ceramic base member 10, and a metal film layer (a circuit layer 20 and a cooling fin 40) formed on a surface of the intermediate layer 50 by accelerating a powder of metal or alloy with a gas and spraying and depositing the powder on the surface of the intermediate layer 50 as the powder is in a solid state.
摘要翻译：当通过使用冷喷涂法制造具有形成在陶瓷基底上的金属膜的层压体时，提供陶瓷和金属膜之间的粘合强度高的层叠体以及这种层压体的制造方法。层叠体包括具有绝缘性的陶瓷基体部件10，在陶瓷基体部件10的表面上形成的金属或合金作为主要成分的中间层50，以及金属膜层（电路层20和冷却翅片40），其通过用气体加速金属或合金粉末而形成在中间层50的表面上，并且当粉末处于固体状态时将粉末喷涂并沉积在中间层50的表面上。

32. 发明公开

EP1237195A3 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：EP1237195A3
公开(公告)日：2012-07-18
申请号：EP02004670.2
申请日：2002-02-28
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Suzawa, Hideomi , Kusuyama, Yoshihiro , Ono, Koji , Koyama, Jun
IPC分类号： H01L27/12 , H01L21/84 , G02F1/1362 , H01L21/77 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L21/4846 , G02F1/13454 , G02F1/13458 , G02F1/136286 , G02F2001/13629 , G02F2001/136295 , H01L21/02367 , H01L27/12 , H01L27/124 , H01L27/1277 , H01L29/42384 , H01L29/4908 , H01L29/78621 , H01L29/78627
摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, amaterial film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 µm or more.
摘要翻译：提供了即使在显示区域的尺寸增大以成为大尺寸屏幕的情况下也实现低功耗的半导体装置的结构及其制造方法。像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜的三层结构，以减小布线电阻。使用IPC蚀刻装置蚀刻布线。栅电极具有锥形形状，成为锥形的区域的宽度被设定为1μm以上。

33. 发明公开

EP2388813A2 Verfahren zur Herstellung von Leistungshalbleitersubstraten 审中-公开
公开(公告)号：EP2388813A2
公开(公告)日：2011-11-23
申请号：EP11162025.8
申请日：2011-04-12
申请人： SEMIKRON Elektronik GmbH & Co. KG
发明人： Göbl, Christian
IPC分类号： H01L23/373 , H05K3/24 , H05K3/38
CPC分类号： H01L23/15 , H01L21/4846 , H01L2924/0002 , H05K1/0306 , H05K3/202 , H05K3/38 , H05K2203/074 , H05K2203/1131 , H01L2924/00
摘要： Es wird ein Verfahren zur Herstellung von Leistungshalbleitersubstraten (12) mit einem isolierenden flächigen Grundkörper (14) beschrieben, der an mindestens einer Hauptfläche (16) eine Schichtenfolge aus einer Sintermetallschicht (18) und einer Leitungsschicht (20) aufweist, durch Druck- und Temperaturbeaufschlagung, wobei das mindestens ein Leistungshalbleitersubstrat (12) mit einem Vergussmaterial (28) umschlossen wird und das mindestens eine mit dem Vergussmaterial (28) umschlossenes Leistungshalbleitersubstrat (12) anschließend in eine mit einer Flüssigkeit (30) gefüllte Druckkammer (10) eingebracht und mit Druck und Temperatur beaufschlagt wird, wobei der Druck an dem mindestens einen Leistungshalbleitersubstrat (12) unverzüglich isostatisch und die Temperatur an dem mindestens einen Leistungshalbleitersubstrat (12) zur stoffschlüssigen Verbindung des Grundkörpers (12) mittels der Sintermetallschicht (18) mit der zugehörigen Leitungsschicht (20) durch das eine definierte Wanddicke besitzende Vergussmaterial (28) zeitlich verzögert wirksam wird.
摘要翻译：用于制造具有绝缘扁平基体（14）的功率半导体衬底（12）的方法，所述绝缘扁平基体（14）具有从烧结金属层（18）和主表面（16）上的导电层（20）的层序，通过压力和温度施加，包括通过铸造材料覆盖半导体衬底，在填充有流体的压力室中进行压力和温度的压力。压力和温度暂时受到半导体衬底的影响，用于通过烧结金属层材料配合连接基体。用于制造具有绝缘扁平基体（14）的功率半导体衬底（12）的方法，所述绝缘扁平基体（14）具有从烧结金属层（18）和主表面（16）上的导电层（20）的层序，通过压力和温度施加，包括通过铸造材料覆盖半导体衬底，在填充有流体的压力室中进行压力和温度的压力。压力和温度暂时受到半导体衬底的影响，用于通过烧结金属层与通过铸造材料的伴随导电层材料配合连接基体。使用硅铸造材料作为铸造材料，烧结矿用于烧结金属层。流体在250℃的压力室中进行，并在38-40MPa的压力下进行。功率半导体基板彼此配置成与铸造材料连接的堆叠。叠层由由硅膜，形成导电层的金属膜，形成烧结金属层的烧结膏，绝缘扁平基体，形成烧结金属层的烧结膏，金属膜形成导电层和硅膜。堆叠被热稳定膜包围，之后用铸造材料进行覆盖。

34. 发明公开

EP2287897A3 Circuit member for semiconductor device, semiconductor device using the same, and process for producing said circuit member and said semiconductor device 失效
标题翻译：用于半导体器件，半导体器件，因而对于该开关元件的制备方法，和该半导体装置的开关元件
公开(公告)号：EP2287897A3
公开(公告)日：2011-11-02
申请号：EP10011870.2
申请日：1997-05-27
申请人： Dai Nippon Printing Co., Ltd.
发明人： Yagi, Hiroshi , Nagasaki, Osamu , Sasaki, Masato
IPC分类号： H01L23/31 , H01L21/56
CPC分类号： H01L21/568 , H01L21/4846 , H01L21/4857 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L2221/68345 , H01L2224/32014 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85001 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/1433 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： The present invention provides a circuit member for a semiconductor device, which comprises: a conductive substrate; and a circuit section and the like at least two-dimensionally formed using a conductive metal by plating on the conductive substrate, the circuit section comprising at least a lead for electrical connection to a semiconductor element and an external terminal section for electrical connection to an external circuit, the circuit section having no die pad section for mounting a semiconductor element thereon, a plurality of sets of the lead and the external terminal section integrally connected to each other being provided independently of each other, at least a part of the conductive metal constituting the circuit section and the like being provided by plating on at least one side of the conductive substrate after subjecting the one side of the conductive substrate to surface treatment to create irregularities and to release treatment to impart releasability.

35. 发明公开

EP2381472A1 Procédé de fabrication d'un dispositif microélectronique et dispositif microélectronique ainsi fabriqué 无效
标题翻译： Herstellungsverfahren einer mikroelektronischen Vorrichtung，und so hergestellte mikroelektronische Vorrichtung
公开(公告)号：EP2381472A1
公开(公告)日：2011-10-26
申请号：EP11163545.4
申请日：2011-04-21
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Hilt, Thierry , Boutry, Hervé , Franiatte, Rémi , Moreau, Stéphane
IPC分类号： H01L21/98 , H01L25/065
CPC分类号： H01L25/0657 , H01L21/4846 , H01L21/56 , H01L23/3107 , H01L23/49811 , H01L24/16 , H01L25/50 , H01L2224/32145 , H01L2225/06524 , H01L2225/06579 , H01L2924/01019 , H01L2924/1461 , H01L2924/00
摘要： L'invention concerne un procédé de fabrication d'un dispositif microélectronique sur un substrat comportant au moins un premier et un second composants électriques répartis, respectivement, dans des premier et second niveaux empilés l'un au-dessus de l'autre sur le substrat, ce procédé comprenant :
- la fabrication (102) d'au moins un premier et un deuxième bras de longueurs différentes, chacun de ces bras reliant mécaniquement directement un plot électrique à un point d'ancrage fixe respectif sur le substrat, et
- le plot électrique est fabriqué à l'intérieur du premier niveau puis déplacé (106), avant le raccordement électrique du second composant, vers une position de connexion dans laquelle une face supérieure du plot électrique et en contact avec l'intérieur du second niveau parallèlement au substrat.
摘要翻译：该方法包括制造其长度和宽度大于其厚度的可移动电垫（40）。电气部件电连接在焊盘的上表面上以将部件与另一电气部件电连接。制造具有不同长度的臂，其中每个臂将垫与固定在基底上的固定点机械连接。在连接前一部件之前，焊盘朝着连接位置移动，在该连接位置，上表面与平行于基板的电平内部接触。电气部件是微电子芯片，即半导体晶片，导体条或电连接器。对于包括衬底的微电子器件还包括独立权利要求。

36. 发明公开

EP2071622A3 Package for semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造
公开(公告)号：EP2071622A3
公开(公告)日：2011-09-07
申请号：EP08171700.1
申请日：2008-12-15
申请人： Shinko Electric Industries Co., Ltd.
发明人： Koizumi, Naoyuki , Oi, Kiyoshi , Tateiwa, Akihiko
IPC分类号： H01L23/498 , H01L21/48 , H01L23/14
CPC分类号： H01L23/142 , H01L21/4846 , H01L23/49822 , H01L2924/0002 , H01L2924/15311 , H05K3/06 , H05K3/4608 , H05K3/4641 , H05K2201/0355 , H05K2203/0369 , H05K2203/0733 , H05K2203/1476 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , H01L2924/00
摘要： In a package for a semiconductor device, a core substrate (12) has two metal plates (20a, 20b), each of which includes a first through hole (16), a second through hole (22), a projection (24), and an insulating layer (26) formed on its surface. The metal plates are stacked in a manner that the projections of the mutual metal plates enter the second through hole of the metal plate on a partner side, and the first through holes of the metal plates form a through hole penetrating the core substrate. A tip end of each of the projections of the metal plates is exposed to a surface of the metal plate on the partner side to form a first terminal portion, and a second terminal portion is exposed from the insulating layer and formed on a surface of the metal plate on a side where the first terminal portion of the metal plate on the partner side is exposed.

37. 发明公开

EP2058859A3 Wiring substrate and semiconductor device and method of manufacturing the same 审中-公开
标题翻译：配线基板和半导体装置及其制造方法
公开(公告)号：EP2058859A3
公开(公告)日：2011-08-24
申请号：EP08166935.0
申请日：2008-10-17
申请人： Shinko Electric Industries Co., Ltd.
发明人： Sunohara, Masahiro , Machida, Yoshihiro
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00
CPC分类号： H01L23/49811 , H01L21/4846 , H01L23/42 , H01L23/49822 , H01L24/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/16152 , H05K1/0271 , H05K1/111 , H05K3/4092 , H05K3/4644 , H05K2201/0133 , H05K2201/0187 , H05K2201/0397 , H05K2201/09036 , H05K2201/10674 , H01L2924/00
摘要： In a wiring substrate (2) of a semiconductor device (1), a hollow portion (H) is provided under a pad wiring portion (23) including a connection pad (P), and thus a wiring layer (24) has a cantilever structure in which the pad wiring portion (23) is formed as an aerial wiring, and a semiconductor chip (40) is flip-chip connected to the connection pad (P). The pad wiring portion (23) including the connection pad (P) is formed on a sacrifice layer (14) which is filled in a recess portion (C) in an interlayer insulating layer (32) of the wiring substrate (2), then the semiconductor chip (40) is flip-chip connected to the connection pad (P), and then the hollow portion (H) is provided by removing the sacrifice layer (14).

38. 发明公开

EP2306501A2 Ceramic wiring board and method of manufacturing thereof 审中-公开
标题翻译： Keramische Leiterplatte und Herstellungsverfahrendafür
公开(公告)号：EP2306501A2
公开(公告)日：2011-04-06
申请号：EP10185725.8
申请日：2010-10-01
申请人： IBIDEN CO., LTD.
发明人： Furuichi, Wataru , Honda, Hirokazu
IPC分类号： H01L21/48 , H01L23/373
CPC分类号： H01L21/4846 , H01L23/3735 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a ceramic wiring board includes steps of: forming a copper layer on a ceramic substrate through a low-temperature growth technique (step S13), increasing a temperature of the copper layer at equal to or higher than an annealing temperature of copper (step S16), and cooling the copper layer after the temperature increasing (step S18).
摘要翻译：陶瓷布线板的制造方法包括以下步骤：通过低温生长技术在陶瓷基板上形成铜层（步骤S13），使铜层的温度升高到铜的退火温度以上（步骤S16），在升温后冷却铜层（步骤S18）。

39. 发明公开

EP2285752A1 CONTINUOUS OR DISCRETE METALLIZATION LAYER ON A CERAMIC SUBSTRATE 审中-公开
标题翻译：在陶瓷基板上连续或离散的金属化层
公开(公告)号：EP2285752A1
公开(公告)日：2011-02-23
申请号：EP09739251.8
申请日：2009-04-30
申请人： Seleznev, Maxim
发明人： Seleznev, Maxim
IPC分类号： C04B37/02
CPC分类号： C04B37/026 , C04B41/009 , C04B41/52 , C04B41/90 , C04B2111/00844 , C04B2235/6565 , C04B2235/96 , C04B2237/124 , C04B2237/366 , C04B2237/407 , C04B2237/54 , C04B2237/706 , H01L21/4846 , H01L23/3735 , H01L2924/0002 , H01L2924/09701 , C04B41/4519 , C04B41/4556 , C04B41/5031 , C04B41/0072 , C04B41/4529 , C04B41/4572 , C04B41/5127 , C04B41/4539 , C04B35/581 , H01L2924/00
摘要： Surface metallization technology for ceramic substrates is disclosed herein. It makes use of a known phenomenon that many metal - metal oxide alloys in liquid state readily wet an oxide ceramic surface and strongly bond to it upon solidification. To achieve high adhesion strength of a metallization to ceramic, a discrete metallization layer consisting of metal droplets bonded to ceramic surface using metal - metal oxide bonding process is produced first. Next, a continuous metal layer is deposited on top of the discrete layer and bonded to it using a sintering process. As a result a strongly adhering, glass-free metallization layer directly bonded to ceramic surface is produced. In particular, the process can be successfully used to metallize aluminum nitride ceramic with high theπnal and electrical conductivity copper metal.

40. 发明公开

EP1990831A3 Multilayer printed circuit board and multilayer printed circuit board manufacturing method 审中-公开
公开(公告)号：EP1990831A3
公开(公告)日：2010-09-29
申请号：EP08161669.0
申请日：2001-01-12
申请人： IBIDEN CO., LTD.
发明人： Sakamoto, H. c/o Ogaki-kita-kojou Ibiden Co., Ltd. , Sugiyama, T. c/o Ogaki-kita-kojou Ibiden Co., Ltd. , Wang, D. c/o Ogaki-kita-kojou Ibiden Co., Ltd. , Kariya, T. c/o Ogaki-kita-kojou Ibiden Co., Ltd.
IPC分类号： H01L23/538 , H01L23/498
CPC分类号： H01L24/29 , H01L21/4846 , H01L21/4857 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/83 , H01L25/03 , H01L25/18 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16227 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/45144 , H01L2224/73267 , H01L2224/83192 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01052 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/18162 , H01L2924/30107 , H05K1/185 , H05K3/4602 , H05K2201/09036 , H05K2201/09563 , H05K2201/096 , H05K2201/09918 , H05K2201/10674 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49133 , Y10T29/49144 , Y10T29/49147 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2224/83 , H01L2224/82 , H01L2924/3512 , H01L2924/00
摘要： A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.

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