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    • 1. 发明公开
    • Semiconductor Device and Manufacturing Method Thereof
    • 半导体器件及其制造方法
    • EP2270849A3
    • 2017-09-06
    • EP10188106.8
    • 2001-03-06
    • Semiconductor Energy Laboratory Co., Ltd.
    • Yamazaki, ShunpeiKoyama, JunSuzawa, HideomiOno, KojiArao, Tatsuya
    • H01L29/423H01L29/49H01L29/786H01L27/12G02F1/1362G02F1/1345
    • H01L27/1222G02F1/13454H01L27/124H01L27/1255H01L27/127H01L29/42384H01L29/4908H01L29/78621H01L2029/7863
    • The invention provides a semiconductor device comprising:
      a semiconductor film over an insulating surface;
      a gate insulating film over the semiconductor film; and
      a gate electrode comprising:
      a first conductive layer over the gate insulating film; and
      a second conductive layer over the first conductive layer;
      wherein the semiconductor film includes,
      a channel forming region,
      LDD regions in contact with the channel forming region,
      a source region and a drain region in contact with the LDD regions,
      wherein an end portion of the first conductive layer extends beyond an end portion of the second conductive layer,
      wherein the LDD regions overlap the first conductive layer with the gate insulating film interposed therebetween,
      wherein the second conductive layer has a tapered shape in the end portion of the second conductive layer in cross section,
      wherein the first conductive layer comprises at least a first element selected from the group consisting of Ta, W, Ti, Mo, AI, and Cu and the second conductive layer comprises at least a second element selected from the group consisting of Ta, W, Ti, Mo, AI, and Cu, and wherein the first element is different from the second element.
    • 本发明提供了一种半导体器件,包括:绝缘表面上的半导体膜; 在半导体膜上的栅极绝缘膜; 以及栅电极,包括:在所述栅绝缘膜上的第一导电层; 以及在第一导电层上的第二导电层; 其中所述半导体膜包括沟道形成区,与所述沟道形成区接触的LDD区,与所述LDD区接触的源极区和漏极区,其中所述第一导电层的端部延伸超出所述LDD区的端部 第二导电层,其中LDD区与第一导电层重叠,其间插入栅极绝缘膜,其中第二导电层在第二导电层的端部中具有锥形形状的横截面,其中第一导电层包括 至少一种选自Ta,W,Ti,Mo,Al和Cu的第一元素,第二导电层至少包括选自Ta,W,Ti,Mo,Al, 和Cu,并且其中第一元素不同于第二元素。
    • 9. 发明公开
    • Signal processing unit with reduced power consumption and method for driving the same
    • Signalverarbeitungsschaltung mit reduziertem Energieverbrauch und Ansteuerverfahrendafür
    • EP2426669A1
    • 2012-03-07
    • EP11179033.3
    • 2011-08-26
    • Semiconductor Energy Laboratory Co., Ltd.
    • Koyama, JunYamazaki, Shunpei
    • G11C14/00
    • G11C14/0054G11C14/00G11C14/0009H01L27/0629
    • An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage element (100) includes two logic elements (referred to as a first phase-inversion element (101) and a second phase-inversion element (102)) which invert a phase of an input signal (IN) and output the signal, a first selection transistor (103), and a second selection transistor (104). In the storage element, two pairs each having a transistor in which a channel is formed in an oxide semiconductor layer and a capacitor (a pair of a first transistor (112) and a first capacitor (122), and a pair of a second transistor (111) and a second capacitor (121)) are provided. The storage element is used in a storage device such as a register or a cache memory included in a signal processing circuit. Reduction of power consumption is achieved by deactivating said first and second transistors.
    • 本发明的目的是提供一种信号处理电路,其可以在没有复杂的制造工艺的情况下制造并且抑制功耗。 存储元件(100)包括反转输入信号(IN)的相位并输出信号的两个逻辑元件(称为第一相位反转元件(101)和第二相位反转元件(102)), 第一选择晶体管(103)和第二选择晶体管(104)。 在存储元件中,每对具有在氧化物半导体层中形成沟道的晶体管和电容器(一对第一晶体管(112)和第一电容器(122))以及一对第二晶体管 (111)和第二电容器(121))。 存储元件用于诸如信号处理电路中包括的寄存器或高速缓冲存储器的存储设备中。 通过停用所述第一和第二晶体管来实现功耗的降低。