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31. 发明公开

EP2159704A4 CASH MEMORY CONTROL DEVICE AND PIPELINE CONTROL METHOD 有权
标题翻译： CACHE存储器控制装置和管道的控制方法
公开(公告)号：EP2159704A4
公开(公告)日：2011-08-31
申请号：EP07790186
申请日：2007-06-20
申请人： FUJITSU LTD
发明人： SHIMIZUNO KOKEN , ISHIMURA NAOYA
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857

32. 发明公开

EP2353058A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
标题翻译： MESOCHRONES SIGNALISIERUNGSSYSTEM MIT TAKTGESTEUERTEM NIEDRIGLEISTUNGSMODUS
公开(公告)号：EP2353058A1
公开(公告)日：2011-08-10
申请号：EP09837752.6
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：集成电路存储器控制器向存储器件输出处于第一状态的第一信号，以使存储器件内的同步数据发送和接收电路能够操作。存储器控制器内的事务队列存储要被服务的存储器读和写请求，分别要求存储器件内的同步数据发送和接收电路的操作。存储器控制器内的电源控制电路确定事务队列已经达到预定状态，并且作为响应，在第二状态下将第一信号输出到存储器件，以禁止存储器件内的同步数据发送和接收电路的操作。

33. 发明公开

EP1990729A1 PROCESSOR DEVICE AND INSTRUCTION PROCESSING METHOD 审中-公开
标题翻译：欧洲经济与社会发展委员会（UNZHORA-EINRICHTUNG UND ANWEISUNGSVERARBEITUNGSVERFAHREN）
公开(公告)号：EP1990729A1
公开(公告)日：2008-11-12
申请号：EP06714758.7
申请日：2006-02-27
申请人： Fujitsu Ltd.
发明人： UKAI, Masaki
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0857 , G06F12/0859
摘要： A large number of requests can be stored irrespective of the buffer capacity of a response side, and the processing efficiency of a CPU core can be improved. A cache (102) receives a request from an instruction execution unit (101), searches for necessary data, outputs the data to the instruction execution unit (101) if there is a cache hit, and instructs a request storage unit (103) to request a move-in of the data if a cache miss occurs. The request storage unit (103) stores therein the request corresponding to the instruction of the cache (102) while the requested process is being executed. A REQID assignment unit (104) reads the request stored in the request storage unit (103), selects an unused REQID from a REQID table (105), and assigns the unused REQID to the read request. The REQID is an identification number of the request based on the number of requests set as the maximum number that can be received at a simultaneous time by a system controller (200) of the response side.
摘要翻译：无论响应侧的缓冲器容量如何，都可以存储大量请求，并且可以提高CPU内核的处理效率。高速缓存（102）从指令执行单元（101）接收请求，搜索必要的数据，如果存在高速缓存命中则将数据输出到指令执行单元（101），并且指示请求存储单元（103）如果发生缓存未命中，则请求数据的移入。请求存储单元（103）在执行所请求的进程时存储对应于高速缓存（102）的指令的请求。 REQID分配单元（104）读取存储在请求存储单元（103）中的请求，从REQID表（105）中选择未使用的REQID，并将未使用的REQID分配给读请求。 REQID是基于响应侧的系统控制器（200）在同一时刻可以接收到的最大数量的请求数量的请求的标识号。

34. 发明公开

EP0398523A3 A device for data i/o and execution support in digital processors 失效
标题翻译：数据处理器中的数据I / O和执行支持的设备
公开(公告)号：EP0398523A3
公开(公告)日：1991-08-21
申请号：EP90304460.0
申请日：1990-04-25
申请人： HITACHI, LTD.
发明人： Patel, Chandravadan N. , Blasco, Richard WM. , Chan, Kenneth M. , Chen, Shieh C.
IPC分类号： G06F13/12 , G06F12/08
CPC分类号： G06F12/0853 , G06F12/0857
摘要： A device for simultaneous data input and output and execution support in digital processors including a plurality of controllable input and output ports (6,8,12) for inputting and outputting data from the device, a data cache memory (10) which is selectively connectable to each of the plurality of input and output ports (6,8,12) and a controller (20) for controlling the plurality of input and output ports (6,8,12) and the data cache memory (10) for effecting a transfer of data between any of the plurality of input and output ports (6,8,12) or the data cache memory (10).

35. 发明公开

EP0150523A2 Data processing system with improved memory system 失效
标题翻译： Datenverarbeitungssystem mit Speichersystem。
公开(公告)号：EP0150523A2
公开(公告)日：1985-08-07
申请号：EP84201483.9
申请日：1981-04-27
申请人： DATA GENERAL CORPORATION
发明人： Druke, Michael B. , Ziegler, Michael L.
IPC分类号： G06F12/06
CPC分类号： G06F12/0661 , G05B19/054 , G06F11/106 , G06F12/0802 , G06F12/0804 , G06F12/0857
摘要： The main memory of a data processing system comprises a plurality of modules, each with four memory planes (60), each storing 16k 39-bit words (32 bits data plus 7 parity bits). Write data is received from a controller on a write data bus (WDO-38) and read data goes to the controller on a read data bus (RDO-38). Up to 16 modules can be selected by fourselecting bits (MOD SELO-3) which are compared by a comparator (66) with the module's own address (MODO-3).
The memory planes are accessed in sequence using seven address bits (ADDRO-5, J ADR 6) latched in address latches (67) in conjunction with a row address strobe (RAS) and a column address strobe (CAS) which strobe in row and column addresses sequentially from the latches to complete the selection of a single word to be written or read. Control logic (65) controls selection of write and read operations in response to signals (LDIN, LDOUT), and refreshing in response to a refresh signal (REFRESH).
摘要翻译：数据处理系统的主存储器包括多个模块，每个模块具有四个存储平面（60），每个模块存储16k 39位字（32位数据加上7个奇偶校验位）。在写数据总线（WDO-38）上从控制器接收写数据，读数据在读数据总线（RDO-38）上传送到控制器。可以通过比较器（66）与模块自己的地址（MODO-3）比较的四个选择位（MOD SELO-3）来选择最多16个模块。存储器平面被顺序地使用锁存在地址锁存器（67）中的七个地址位（ADDRO-5，J ADR 6）以及行地址选通（RAS）和列地址选通（CAS）进行访问，列地址选通（CAS）列从锁存器顺序地寻址以完成要写入或读取的单个字的选择。控制逻辑（65）控制响应于信号（LDIN，LDOUT）的写入和读取操作的选择以及响应于刷新信号（REFRESH）的刷新。

36. 发明公开

EP0046781A4 CACHED MULTIPROCESSOR SYSTEM WITH PIPELINE TIMING. 失效
标题翻译：与高速缓存存储器和处理多处理器系统重叠。
公开(公告)号：EP0046781A4
公开(公告)日：1984-06-13
申请号：EP81900540
申请日：1981-01-28
申请人： DIGITAL EQUIPMENT CORP
发明人： ARULPRAGASAM JEGA A , GIGGI ROBERT A , LARY RICHARD F , SULLIVAN DANIEL T
IPC分类号： G06F15/16 , G06F9/46 , G06F12/08 , G06F12/14 , G06F13/18 , G06F13/20 , G06F15/167 , G06F15/177 , G06F15/80 , G06F9/38
CPC分类号： G06F9/52 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/1458 , G06F13/18 , G06F15/177
摘要： A multiprocessor data processing system including a main memory system, the processors (30) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), for accessing copies of memory data therein without undue delay in retrieving data from the main memory system. A synchronous processor bus (76) having conductors (104) couples the processors (30) to the CCU. An asynchronous input/output bus (60) couples input/output devices (32) to an interface circuit (64) which, in turn, couples the information signals thereof to the synchronous processor bus (76) of the CCU so that both the processors (30) and the I/O devices (32) can gain quick access to memory data rather than in the cache memory (20). When a read command "misses" the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). To inhibit reads to locations in the cache for which there is a write-in-progress, the CCU includes a Processor Index random-access-memory (PIR 20) that temporarily stores memory addresses for which there is a write-in-progress. The PIR is used by the cache memory to force a "miss" for all references to the memory address contained therein until the CCU updates the cache memory. The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a main memory location that is to be maintained in the cache memory.

37. 发明公开

EP0046781A1 CACHED MULTIPROCESSOR SYSTEM WITH PIPELINE TIMING 失效
标题翻译：与高速缓存存储器和处理多处理器系统重叠。
公开(公告)号：EP0046781A1
公开(公告)日：1982-03-10
申请号：EP81900540.0
申请日：1981-01-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： ARULPRAGASAM, Jega A. , GIGGI, Robert A. , LARY, Richard F. , SULLIVAN, Daniel T.
IPC分类号： G06F15 , G06F9 , G06F12 , G06F13
CPC分类号： G06F9/52 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/1458 , G06F13/18 , G06F15/177
摘要： Systeme multi processeur de traitement de donnees comprenant un systeme de memoire principale, dont les processeurs (30) partagent une unite de commande commune (CCU 10) qui comprend une antememoire (20) d'ecriture intermediaire, pour acceder a des copies de donnees en memoire en evitant un retard exagere dans l'extraction de donnees du systeme de memoire principale. Un bus (76) de processeur synchrone possedant des conducteurs (104) relie le processeur (30) au CCU. Un bus (60) d'entree/sortie asynchrone relie les dispositifs (32) d'entree/sortie a un circuit (64) d'interface qui, a son tour, relie les signaux d'information au bus (76) de processeur synchrone du CCU de maniere que les processeurs (30) et les dispositifs (32) d'entree/sortie puissent acceder rapidement aux donnees en memoire plutot qu'a celles contenues dans l'antememoire (20). Lorsqu'une commande "manque" l'antememoire (20), le CCU accede aux modules (28) de memoire pour attribuer son antememoire (20) et renvoyer les donnees lues aux processeurs (30) ou au dispositif (32) d'entree/sortie. Pour inhiber la lecture d'adresses dans l'antememoire ou une phase d'ecriture est en cours, le CCU comprend une memoire (PIR 20) a acces sequentiel d'index de processeur qui stocke temporairement les adresses de memoire ou une phase d'ecriture est en cours. Le PIR est utilise par l'antememoire de maniere a forcer un "coup manque" pour toutes les references a l'adresse de memoire contenue dans le PIR juste au moment ou le CCU remet a jour l'antememoire. Le CCU comprend aussi un double de memoire d'adresse symbolique (67) qui garde une copie de l'adresse symbolique de l'antememoire (20A) de maniere a permettre au CCU de remettre a jour son antememoire lorsque la donnee est ecrite a une adresse de la memoire principale devant etre maintenue dans l'antememoire.

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