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31. 发明公开

EP2261804A1 Cache controller and cache control method 审中-公开
标题翻译： Cache-steuerung和Cache-steuerverfahren
公开(公告)号：EP2261804A1
公开(公告)日：2010-12-15
申请号：EP10174845.7
申请日：2006-02-27
申请人： FUJITSU LIMITED
发明人： Ukai, Masaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0844 , G06F12/0857 , G06F12/0859 , G06F2212/1016 , G06F2212/1056
摘要： A cache controller that writes data to a cache memory, (111) comprises: a first buffer unit (102) that retains data flowing in from outside to be written to the cache memory (111); a second buffer unit (108) that has a plurality of divided areas, each of the divided areas respectively retaining a data piece to be currently written to the cache memory (111), among pieces of the data retained in the first buffer unit (102); a monitoring unit (106) that monitors the divided areas of the second buffer unit (108) and reports whether the second buffer unit (108) has an available divided area; and an input and output controller (105) that controls the first buffer unit (102) to output the data piece to be currently written to the cache memory (111) to the second buffer unit (108) when it is reported by the monitoring unit (106) that the second buffer unit (108) has an available divided area.
摘要翻译：一种将数据写入高速缓冲存储器的缓存控制器，包括：第一缓冲单元，保存从外部流入的数据，以写入高速缓冲存储器; 具有多个分割区域的第二缓冲器单元（108），每个分割区域分别保留在第一缓冲单元（102）中保留的数据中的当前写入高速缓冲存储器（111）的数据段）; 监视单元（106），其监视所述第二缓冲器单元（108）的划分区域并且报告所述第二缓冲单元（108）是否具有可用划分区域; 以及输入和输出控制器（105），当所述监视单元报告所述控制器（105）时，所述输入和输出控制器（105）控制所述第一缓冲器单元（102）将当前写入所述高速缓冲存储器（111）的数据片段输出到所述第二缓冲器单元（106）所述第二缓冲单元（108）具有可用的分割区域。

32. 发明公开

EP2159704A1 CASH MEMORY CONTROL DEVICE AND PIPELINE CONTROL METHOD 有权
标题翻译： CACHE-SPEICHERSTEUEREINRICHTUNG UND PIPELINE-STEUERVERFAHREN
公开(公告)号：EP2159704A1
公开(公告)日：2010-03-03
申请号：EP07790186.6
申请日：2007-06-20
申请人： Fujitsu Limited
发明人： SHIMIZUNO, Koken , ISHIMURA, Naoya
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857
摘要： With a view to reducing the congestion of a pipeline for cache memory access in, for example, a multi-core system, a cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.
摘要翻译：为了减少例如多核系统中的高速缓冲存储器访问的流水线的拥塞，高速缓冲存储器控制装置包括：确定单元，用于确定从例如每个核心提供的命令是在执行命令期间访问缓存内存; 以及路径切换单元，用于将被确定为访问高速缓冲存储器的命令置于流水线处理中，并且将未被确定为不访问高速缓冲存储器的命令直接输出到外部单元，而不将命令输入流水线处理。

33. 发明公开

EP1990730A4 CACHE CONTROLLER AND CACHE CONTROL METHOD 有权
标题翻译：高速缓存控制器和缓存控制方法
公开(公告)号：EP1990730A4
公开(公告)日：2009-07-08
申请号：EP06714759
申请日：2006-02-27
申请人： FUJITSU LTD
发明人： UKAI MASAKI
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0844 , G06F12/0857 , G06F12/0859 , G06F2212/1016 , G06F2212/1056
摘要： The size and cost of a chip are reduced, and much data to be written in a cache memory is captured. An external bus control section (101) inputs MI data from an external bus into an MI data RAM (102) at a timing corresponding to the control of an input/output control section (105). The MI data RAM (102) stores the MI data and output the MI data to a data register section (108) through a selector (104) when a free area occurs in the data register section (108). The input/output control section (105) inputs the MI data inputted into the external bus control section (101) into the MI data RAM (102) according to the CPU cycle. The data register section (108) temporarily captures the MI data to be written in an L2 cache (111) and writes it in the L2 cache (111).

34. 发明授权

EP0046781B1 CACHED MULTIPROCESSOR SYSTEM WITH PIPELINE TIMING 失效
标题翻译：具有管道时序的缓存多处理器系统
公开(公告)号：EP0046781B1
公开(公告)日：1988-03-30
申请号：EP81900540.6
申请日：1981-01-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： ARULPRAGASAM, Jega A. , GIGGI, Robert A. , LARY, Richard F. , SULLIVAN, Daniel T.
IPC分类号： G06F12/08 , G06F13/18 , G06F12/14 , G06F15/16
CPC分类号： G06F9/52 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/1458 , G06F13/18 , G06F15/177
摘要： A multiprocessor data processing system including a main memory system, the processors (30) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), for accessing copies of memory data therein without undue delay in retrieving data from the main memory system. A synchronous processor bus (76) having conductors (104) couples the processors (30) to the CCU. An asynchronous input/output bus (60) couples input/output devices (32) to an interface circuit (64) which, in turn, couples the information signals thereof to the synchronous processor bus (76) of the CCU so that both the processors (30) and the I/O devices (32) can gain quick access to memory data rather than in the cache memory (20). When a read command "misses" the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). To inhibit reads to locations in the cache for which there is a write-in-progress, the CCU includes a Processor Index random-access-memory (PIR 20) that temporarily stores memory addresses for which there is a write-in-progress. The PIR is used by the cache memory to force a "miss" for all references to the memory address contained therein until the CCU updates the cache memory. The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a main memory location that is to be maintained in the cache memory.

35. 发明公开

EP0150523A3 DATA PROCESSING SYSTEM WITH IMPROVED MEMORY SYSTEM 失效
标题翻译：具有改进的存储器系统的数据处理系统
公开(公告)号：EP0150523A3
公开(公告)日：1986-12-30
申请号：EP84201483
申请日：1981-04-27
申请人： DATA GENERAL CORPORATION
发明人： DRUKE, MICHAEL B. , ZIEGLER, MICHAEL L.
IPC分类号： G05B19/05 , G06F11/10 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0661 , G05B19/054 , G06F11/106 , G06F12/0802 , G06F12/0804 , G06F12/0857
摘要： The main memory of a data processing system comprises a plurality of modules, each with four memory planes (60), each storing 16k 39-bit words (32 bits data plus 7 parity bits). Write data is received from a controller on a write data bus (WDO-38) and read data goes to the controller on a read data bus (RDO- 38). Up to 16 modules can be selected by fourselecting bits (MOD SELO-3) which are compared by a comparator (66) with the module's own address (MODO-3).
The memory planes are accessed in sequence using se ven address bits (ADDRO-5, J ADR 6) latched in address latches (67) in conjunction with a row address strobe (RAS) and a column address strobe (CAS) which strobe in row and column addresses sequentially from the latches to complete the selection of a single word to be written or read. Control logic (65) controls selection of write and read operations in re sponse to signals (LDIN, LDOUT), and refreshing in response to a refresh signal (REFRESH).

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