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21. 发明公开

EP3159816A4 METHOD AND DEVICE FOR CHIP INTEGRATION AND STORAGE MEDIUM 审中-公开
标题翻译： VERFAHREN UND VORRICHTUNG ZUR CHIPENEGRATION SOWIE SPEICHERMEDIUM
公开(公告)号：EP3159816A4
公开(公告)日：2017-07-19
申请号：EP14896824
申请日：2014-11-18
申请人： SANECHIPS TECH CO LTD
发明人： ZHANG QING , GAO CHONGXING
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5045 , G06F2217/06
摘要： A method for chip integration is disclosed. The method includes: inputting the parameter file information of a parameter file required to be searched; obtaining a sub-module port list according to the input parameter file information; carrying out the connection between module ports and / or sub-module ports according to the obtained sub-module port list and a pre-configured netlist; and generating a top level file according to the connection between the module ports and / or the sub-module ports, so as to realize the chip integration. A device for chip integration and a storage medium are disclosed as well.
摘要翻译：公开了一种用于芯片集成的方法。该方法包括：输入需要搜索的参数文件的参数文件信息; 根据输入的参数文件信息获取子模块端口列表; 根据获取的子模块端口列表和预先配置的网表执行模块端口和/或子模块端口之间的连接; 根据模块端口和/或子模块端口之间的连接生成顶层文件，从而实现芯片集成。还公开了一种芯片集成装置和存储介质。

22. 发明公开

EP3182631A1 CARRIER AGGREGATION DEVICE 有权
标题翻译： TRÄGERAGGREGATIONSVORRICHTUNG
公开(公告)号：EP3182631A1
公开(公告)日：2017-06-21
申请号：EP14899819
申请日：2014-12-08
申请人： SANECHIPS TECH CO LTD
发明人： LIU HAIGUANG
IPC分类号： H04L5/00
CPC分类号： H04L5/001 , H04B1/005 , H04L5/00 , H04L5/14
摘要： Disclosed is a carrier aggregation device. The device comprises: a first transceiver antenna, a second transceiver antenna, a first radio frequency front end, a second radio frequency front end, and a radio frequency transceiver chip. A signal received by the first transceiver antenna is divided into a high frequency signal, an intermediate frequency signal and a low frequency signal through the first radio frequency front end, and the three signals separately enter the radio frequency transceiver chip. A signal received by the second transceiver antenna is divided into high frequency signal, an intermediate frequency signal and a low frequency signal through the second radio frequency front end, and the three signals separately enter the radio frequency transceiver chip.
摘要翻译：公开了载体聚集装置。该装置包括：第一收发器天线，第二收发器天线，第一射频前端，第二射频前端和射频收发器芯片。由第一收发天线接收的信号通过第一射频前端分为高频信号，中频信号和低频信号，三个信号分别进入射频收发芯片。由第二收发天线接收的信号通过第二射频前端分为高频信号，中频信号和低频信号，三个信号分别进入射频收发芯片。

23. 发明公开

EP3171576A4 METHOD AND DEVICE FOR TRANSLATION BETWEEN IPV4 AND IPV6 有权
标题翻译： VERFAHREN UND VORRICHTUNG ZURÜBERSETZUNGZWISCHEN IPV4 UND IPV6
公开(公告)号：EP3171576A4
公开(公告)日：2017-06-21
申请号：EP14881531
申请日：2014-11-18
申请人： SANECHIPS TECH CO LTD
发明人： SHI SHENG , SUN QUAN , YAN JUNHUA
IPC分类号： H04L29/12 , H04L29/08
CPC分类号： H04L69/167 , H04L12/4633 , H04L45/74 , H04L45/741 , H04L61/1511 , H04L61/251 , H04L61/2542 , H04L61/6013 , H04L67/2823
摘要： A method for the translation between IPv4 and IPv6 is disclosed, including: a BIH link tracker and quick translator are provided in a network core and when a link is established between an IPv4 client and IPv6 server, a standard translator translates and sends to the IPv6 server, a packet sent from the IPv4 client to the IPv6 server, and the BIH link tracker extracts and records information on link and translation of the IPv4 client and IPv6 server from the packet for interaction therebetween; and during a process of sending the packet after establishing the link between the IPv4 client and IPv6 server, the packet is sent to the quick translator which translates and sends the packet according to the information on the translation corresponding to the information on the link recorded by the BIH link tracker. A device for the translation between IPv4 and IPv6 is also disclosed.
摘要翻译：公开了一种在IPv4和IPv6之间进行翻译的方法，包括：在网络核心中提供BIH链接跟踪器和快速翻译器，并且当在IPv4客户端和IPv6服务器之间建立链接时，标准翻译器翻译并发送到IPv6 服务器发送从IPv4客户端发送到IPv6服务器的分组，并且BIH链路跟踪器从分组中提取并记录关于IPv4客户端和IPv6服务器的链接和翻译的信息以用于它们之间的交互; 并且在建立IPv4客户端与IPv6服务器之间的链路后发送报文的过程中，将报文发送给快速翻译器，快速翻译器根据所记录的链路上的信息对应的翻译信息进行翻译并发送 BIH链接跟踪器。还公开了一种用于在IPv4和IPv6之间进行翻译的设备。

24. 发明公开

EP3160076A4 SEQUENCE DETECTION METHOD AND DEVICE, AND COMPUTER STORAGE MEDIUM 有权
标题翻译： SEQUENZDETEKTIONSVERFAHREN UND -VORRICHTUNG SOWIE COMPUTERSPECHERMEDED
公开(公告)号：EP3160076A4
公开(公告)日：2017-05-31
申请号：EP14896875
申请日：2014-11-03
申请人： SANECHIPS TECH CO LTD
发明人： HE KAIJIANG , PENG JUNFENG
IPC分类号： H04J3/06 , H04L25/14
CPC分类号： H04W56/0015 , H04J3/0608 , H04L25/14 , H04W72/0446
摘要： The disclosure discloses a sequence detection method and apparatus, and a computer storage medium. The method includes: acquiring i-path data with the degree of parallelism i; storing x-th i-path data; receiving (x+1)-th i-path data; forming an x-th detection data set by the x-th i-path data and the (x+1)-th i-path data; extracting s paths of data continuously distributed in the detection data set within each of n detection windows to form n data segments; performing a correlation operation between each data segment and a local sequence; and determining, according to a result of the correlation operation, whether a data segment is a target sequence, wherein x is an integer not less than 1, i is an integer not less than 2, n is less than or equal to i, and s is an integer not less than 1 and equal to a bit number of the target sequence.
摘要翻译：本发明公开了一种序列检测方法和装置以及计算机存储介质。该方法包括：以并行度i获取i路径数据; 存储第x个i路径数据; 接收第（x + 1）个i路径数据; 由第x个i路径数据和第（x + 1）个i路径数据形成第x个检测数据集; 提取连续分布在n个检测窗口中的每个检测窗口内的检测数据集中的s个路径以形成n个数据段; 执行每个数据段与本地序列之间的相关操作; 根据所述关联运算的结果，确定数据片段是否为目标序列，其中x为不小于1的整数，i为不小于2的整数，n小于或等于i， s是不小于1的整数并且等于目标序列的比特数。

25. 发明公开

EP3163777A1 MULTI-CHANNEL SYNCHRONISATION METHOD, SYNCHRONISATION DEVICE AND SYSTEM, AND COMPUTER STORAGE MEDIUM 审中-公开
标题翻译： VERFAHREN ZUR MEHRKANALIGEN SYNCHRONISIERUNG，SYNCHRONISIERUNGSVORRICHTUNG UND-SYSTEM SYSTEM SOWIE COMPUTERSPECHERMEDED
公开(公告)号：EP3163777A1
公开(公告)日：2017-05-03
申请号：EP14896786
申请日：2014-10-31
申请人： SANECHIPS TECH CO LTD
发明人： HE KAIJIANG , PENG JUNFENG
IPC分类号： H04J3/06 , H04L7/00
CPC分类号： H04J3/0658 , H04B10/60 , H04L25/14 , H04L69/22
摘要： Disclosed are a multi-lane synchronization method and apparatus. The method includes: forming N data frames, frame headers of the N data frames including an identical frame header sequence, N being greater than or equal to 1 and less than or equal to the number of lanes M, and M being an integer not less than 2; and sending the N data frames via N lanes, wherein different data frames are sent via different lanes, and the frame header sequence is configured to perform frame synchronization between a receiving end and a sending end or to check frame synchronization. Also disclosed are a synchronization system and a computer storage medium.
摘要翻译：公开了一种多车道同步方法和装置。该方法包括：形成N个数据帧，所述N个数据帧的帧头包括相同的帧头序列，N大于等于1且小于或等于通道数M，M为不小于整数的整数比2; 并通过N个通道发送N个数据帧，其中不同的数据帧通过不同的通道发送，帧头序列用于在接收端和发送端之间进行帧同步或者校验帧同步。还公开了同步系统和计算机存储介质。

26. 发明公开

EP3139560A4 PACKET PROCESSING METHOD, DEVICE AND COMPUTER STORAGE MEDIUM 有权
标题翻译：伏特加福音电脑
公开(公告)号：EP3139560A4
公开(公告)日：2017-04-26
申请号：EP14890824
申请日：2014-09-30
申请人： SANECHIPS TECH CO LTD
发明人： CHEN QINSHU
IPC分类号： H04L29/06 , H04L12/24 , H04L12/723
CPC分类号： H04L47/2466 , H04L29/06 , H04L41/00 , H04L43/0882 , H04L43/16 , H04L45/50 , H04L47/31 , H04L69/22
摘要： Disclosed is a packet processing method, including: determining a type of a packet according to a parsed packet; extracting a characteristics field of the packet according to the determined type of the packet; determining a user-defined keyword corresponding to the packet and a threshold interval of the user-defined keyword according to the characteristics field; determining an OAM type of the packet according to the determined type of the packet, the user-defined keyword corresponding to the packet and the threshold interval of the user-defined keyword; and performing a corresponding OAM operation on the packet according to the determined OAM type; also disclosed are a packet processing device and a computer storage medium.
摘要翻译：公开了一种分组处理方法，包括：根据解析分组确定分组的类型; 根据确定的分组类型提取分组的特征字段; 根据特征字段确定与分组对应的用户定义的关键字和用户定义的关键字的阈值间隔; 根据确定的分组类型确定分组的OAM类型，对应于分组的用户定义关键字和用户定义关键字的阈值间隔; 并根据确定的OAM类型对分组进行相应的OAM操作; 还公开了一种分组处理装置和计算机存储介质。

27. 发明公开

EP3082046A4 DATA ERROR CORRECTING METHOD AND DEVICE, AND COMPUTER STORAGE MEDIUM 有权
标题翻译： VERFAHREN UND VORRICHTUNG ZUR DATENFEHLERKORREKTUR UND COMPUTERSPEICHERMEDIUM
公开(公告)号：EP3082046A4
公开(公告)日：2017-03-08
申请号：EP14876707
申请日：2014-05-20
申请人： SANECHIPS TECH CO LTD
发明人： HUANG YIYUAN
IPC分类号： G06F11/10 , H03M13/19
CPC分类号： H03M13/2906 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1004 , G06F11/1068 , G11C29/52 , H03M13/098 , H03M13/19
摘要： Provided are a data error correcting method and device, and computer storage medium, the method comprising: respectively setting an index number for each data bit, and generating a first check code according to the index number; and generating a second check code according to the first check code, comparing the first check code with the second check code to determine an erroneous data bit, and correcting the erroneous data bit. The device comprises: a setting module configured to respectively set the index number for each data bit; a first check code generation module configured to generate the first check code according to the index number; a second check code generation module configured to generate the second check code according to the first check code; and a data processing module configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit.
摘要翻译：提供了一种数据纠错方法和装置以及计算机存储介质，该方法包括：分别为每个数据位设置索引号，并根据索引号产生第一校验码; 以及根据所述第一校验码生成第二校验码，将所述第一校验码与所述第二校验码进行比较以确定错误的数据位，以及校正所述错误数据位。该设备包括：设置模块，被配置为分别设置每个数据比特的索引号; 第一校验码生成模块，被配置为根据所述索引号生成所述第一校验码; 第二检验码生成模块，被配置为根据第一检验码产生第二检验码; 以及数据处理模块，被配置为将所述第一校验码与所述第二校验码进行比较，以确定错误的数据位，并校正所述错误数据位。

28. 发明公开

EP3091434A4 CHIP STARTING METHOD, MULTI-CORE PROCESSOR CHIP AND STORAGE MEDIUM 有权
标题翻译： CHIPSTARTVERFAHREN，MULTIKERNPROZESSORCHIP UND SPEICHERMEDIUM
公开(公告)号：EP3091434A4
公开(公告)日：2017-01-25
申请号：EP14877078
申请日：2014-04-14
申请人： SANECHIPS TECH CO LTD
发明人： HONG SIHUA , WANG BALING
IPC分类号： G06F9/445 , G06F9/44 , G06F13/30
CPC分类号： G06F9/4401 , G06F9/4405 , G06F13/30 , G06F2213/0038
摘要： A chip starting method, a multi-core processor chip and a storage medium. The chip starting method comprises: setting a first starting priority for more than two processors, and separately setting, for each processor, a second priority of starting each storage unit in more than two storage units; determining, according to the first priority, a first processor that is to be started and has the highest priority; the first processor successively loading a start program from each storage unit according to the second priority corresponding to the first processor, and executing the start program to perform an initialization operation; ending program loading of the first processor when loading of the start program from any storage unit in the more than two storage units succeeds, or loading of the start program from all storage units in the more than two storage units fails; and starting program loading of the second processor and so on until program loading of the more than two processors is completed.
摘要翻译：芯片启动方法，多核处理器芯片和存储介质。芯片启动方法包括：为多于两个处理器设置第一起始优先级，并且为每个处理器分别设置在多于两个存储单元中启动每个存储单元的第二优先级; 根据第一优先级确定要启动且具有最高优先级的第一处理器; 第一处理器根据与第一处理器相对应的第二优先级从每个存储单元连续地加载起始程序，并且执行起始程序以执行初始化操作; 在两个以上的存储单元中的任何存储单元加载起始程序成功时，结束第一处理器的程序加载，或者来自两个以上的存储单元中的所有存储单元的启动程序的加载失败; 并启动第二处理器的程序加载等，直到完成多于两个处理器的程序加载。

29. 发明公开

EP3089411A4 DATA FORWARDING METHOD AND APPARATUS BASED ON INDEXED ALLOCATION 审中-公开
标题翻译：基于索引的分配数据传输方法和设备
公开(公告)号：EP3089411A4
公开(公告)日：2016-12-14
申请号：EP14873797
申请日：2014-05-20
申请人： SANECHIPS TECH CO LTD
发明人： CHEN WEI , BU FANJIN , YANG YONGPENG
IPC分类号： H04L12/741
CPC分类号： H04L45/7453 , H04L45/7457 , H04L47/24

30. 发明公开

EP3328018A4 PACKET SLICING METHOD AND APPARATUS, AND COMPUTER-READABLE MEDIUM 有权
公开(公告)号：EP3328018A4
公开(公告)日：2018-07-04
申请号：EP16827106
申请日：2016-05-30
申请人： SANECHIPS TECH CO LTD
发明人： SHEN YAMING
IPC分类号： H04L29/06
CPC分类号： H04L29/06 , H04L69/22
摘要： Provided are a method and apparatus, and a computer-readable medium for packet slicing, comprising: performing a start of packet (SOP) detection on a data packet to obtain a first detection result; when the SOP detection result indicates that the data packet satisfies a condition for inserting a first burst control word, inserting the first burst control word and filling data control words, each corresponding to an interface bit width, in a unit of the interface bit width; performing an intermediate detection on the data packet to obtain a second detection result; when the second detection result indicates that the data packet satisfies a condition for inserting a second burst control word, inserting the second burst control word, and filling one or more data control words, each corresponding to an interface bit width, in a unit of the interface bit width; performing a packet tail mark detection on the data packet to obtain a third detection result; and inserting, when the third detection result indicates that the data packet has a packet tail mark, fixed number of idle control words.

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