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11. 发明公开

EP1987541A1 DOUBLE-GATE SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：盖茨双门半导体器件具有产生不同的工作功能和处理
公开(公告)号：EP1987541A1
公开(公告)日：2008-11-05
申请号：EP07705775.0
申请日：2007-02-02
申请人： NXP B.V.
发明人： VAN DAL, Mark , SURDEANU, Radu
IPC分类号： H01L29/786 , H01L29/423 , H01L29/49
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/42384 , H01L29/4908 , H01L29/7856
摘要： A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal suicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.
摘要翻译：提供了用于其制造的双栅极FinFET和方法。与FinFET包括第一和第二栅极（72,74）相邻的两侧respectivement翅片（20）的面向所述翅片形成多晶硅的第一栅极的至少一部分，并且面对所述第二栅极的至少一部分翅片形成金属硅化物化合物。两个栅极的不同组合物提供了不同的工作respectivement功能，以降低短沟道效应。

12. 发明公开

EP1966820A2 SOURCE AND DRAIN FORMATION IN SILICON ON INSULATOR DEVICE 审中-公开
标题翻译：硅对器件隔离流入和流出FORM
公开(公告)号：EP1966820A2
公开(公告)日：2008-09-10
申请号：EP06842460.5
申请日：2006-12-12
申请人： NXP B.V.
发明人： SURDEANU, Radu , VAN DAL, Mark
IPC分类号： H01L21/336 , H01L29/417 , H01L29/786 , H01L21/20 , H01L21/285
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28088 , H01L21/28097 , H01L21/28518 , H01L29/41775 , H01L29/66636 , H01L29/78654
摘要： A silicon on insulator device has a silicon layer ( 10 ) over a buried insulating layer ( 12 ). A nickel layer is deposited over a gate ( 16 ), on sidewall spacers ( 22 ) on the sides of the gate ( 16 ), and in a cavity on both sides of the gate ( 16 ) in the silicon layer ( 10 ). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon ( 40 ) over the sidewall spacers ( 22 ) and gate ( 16 ), but where the nickel is adjacent to single crystal silicon ( 10 ) a layer of NiSi ( 44 ) migrates to the surface leaving doped single crystal silicon ( 42 ) behind, forming in one step a source, drain, and source and drain contacts.

13. 发明授权

EP2966792B1 ULTRA-SOUND COMMUNICATION SYSTEM 有权
标题翻译：超声波通信系统
公开(公告)号：EP2966792B1
公开(公告)日：2018-05-16
申请号：EP15172494.5
申请日：2015-06-17
申请人： NXP B.V.
发明人： VAN BEEK, Jozef , SURDEANU, Radu , WIDDERSHOVEN, Franciscus , GAMAND, Patrice , JOS, Rik , DAALDEROP, Gerardo , RIJNS, Hans
IPC分类号： H04B11/00
CPC分类号： G06Q20/401 , G01S3/802 , G01S11/14 , G06K7/10297 , G06Q20/3278 , G06Q20/382 , H04B11/00
摘要： A device is disclosed. The device includes a plurality of microphones to receive ultra-sound signals, wherein the ultra-sound signals include an encoded data. The device also includes a microcontroller coupled to the plurality of microphones. The microcontroller is configured to detect the ultra-sound signals through the plurality of microphones. The detection of the ultra-sound signals includes calculating an angle of arrival of the ultra-sound signals at a microphone in the plurality of microphones. The microcontroller is configured to perform a transaction based on the encoded data received via a microphone in the plurality of microphones.

14. 发明授权

EP2313810B1 DISPLAY DEVICE 失效
标题翻译：显示设备
公开(公告)号：EP2313810B1
公开(公告)日：2017-09-13
申请号：EP09786723.8
申请日：2009-07-27
申请人： NXP B.V.
发明人： BATAILLOU, Benoit , SURDEANU, Radu , BANCKEN, Pascal , STEENWINCKEL, David, van , NGUYEN HOANG, Viet
IPC分类号： G02F1/23 , G02F1/19
CPC分类号： G02F1/19 , G02F1/0147 , G02F1/23 , G02F2203/10 , G09G2300/00

15. 发明授权

EP2269223B1 INTEGRATED CIRCUIT MANUFACTURING METHOD 有权
标题翻译：方法制造集成电路
公开(公告)号：EP2269223B1
公开(公告)日：2013-03-13
申请号：EP09731934.7
申请日：2009-04-14
申请人： NXP B.V.
发明人： NGUYEN HOANG, Viet , SURDEANU, Radu , BATAILLOU, Benoit
IPC分类号： H01L21/311
CPC分类号： H01L27/14685 , H01L21/31053 , H01L21/31111 , H01L27/14621 , H01L27/14629

16. 发明授权

EP2253013B1 Method for fabricating a finfet with separate gates 有权
标题翻译： Verfahren zu Herstellung eines FinFETS mit getrennten Gates
公开(公告)号：EP2253013B1
公开(公告)日：2011-07-20
申请号：EP09711153.8
申请日：2009-02-09
申请人： NXP B.V.
发明人： SONSKY, Jan , SURDEANU, Radu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.
摘要翻译：本发明涉及具有分离栅极的FinFET及其制造方法。在第一和第二栅电极之间的电介质栅极分隔层在从第一栅极层到第二栅极层的方向上延伸，其小于翅片在其相对侧面之间的横向延伸。该结构对应于从具有连续的第一栅极层的覆盖的基本FinFET结构开始的处理方法，并且通过到栅极层的接触开口去除第一栅极层和第一栅极隔离层的部分。随后，替代栅极隔离层同时形成栅极分离层，随后用替换栅极层和金属填充物填充隧道。

17. 发明公开

EP2272304A2 LUMINESCENT COMPONENT AND MANUFACTURING METHOD 审中-公开
标题翻译：照明装置及方法
公开(公告)号：EP2272304A2
公开(公告)日：2011-01-12
申请号：EP09719995.4
申请日：2009-03-09
申请人： NXP B.V.
发明人： NGUYEN HOANG, Viet , SURDEANU, Radu , BATAILLOU, Benoit
IPC分类号： H05B33/10 , H01L33/00
CPC分类号： H05B33/10 , Y10T428/24298 , Y10T428/24331
摘要： The present invention relates to a luminescent component (30) and a manufacturing method thereof. The luminescent component (30) comprises a first transparent carrier (18), a second transparent carrier (24), a substrate (10) sandwiched between said transparent carriers (18; 24), the substrate (10) comprising a conduit from the first transparent layer (18) to the second transparent carrier (24), the conduit being filled with a luminescent solution (20). This facilitates the use of colloidal solutions of quantum dots in such a luminescent component (30). Preferably, the substrate (10) is direct bonded to the transparent carriers (18, 24) using direct wafer bonding techniques.

18. 发明公开

EP2245904A2 SYSTEM AND METHOD FOR ESTIMATING THE JUNCTION TEMPERATURE OF A LIGHT EMITTING DIODE 审中-公开
标题翻译： SYSTEM AND METHOD FOR THE估算温障的发光二极管
公开(公告)号：EP2245904A2
公开(公告)日：2010-11-03
申请号：EP09706157.6
申请日：2009-01-27
申请人： NXP B.V.
发明人： NGUYEN HOANG, Viet , SURDEANU, Radu , BANCKEN, Pascal , BATAILLOU, Benoit , VAN STEENWINCKEL, David
IPC分类号： H05B33/08
CPC分类号： H05B33/0818 , G01K7/01 , H05B33/0866 , H05B33/089
摘要： A method of estimating the junction temperature of a light emitting diode comprises driving a forward bias current through the diode, the current comprising a square wave which toggles between high and low current values (Ihigh, llow), the high current value (lhigh) comprising an LED operation current, and the low current value (ILOW) comprising a non-zero measurement current. The forward bias voltage drop (Vf) is sampled and the forward bias voltage drop (Vflow) is determined at the measurement current (ILOW)-The temperature is derived from the determined forward bias voltage drop.

19. 发明公开

EP2118932A2 I-MOSFET MANUFACTURING METHOD 审中-公开
标题翻译：我MOSFET工艺
公开(公告)号：EP2118932A2
公开(公告)日：2009-11-18
申请号：EP07849529.8
申请日：2007-12-31
申请人： NXP B.V.
发明人： SURDEANU, Radu
IPC分类号： H01L29/739 , H01L21/329
CPC分类号： H01L29/6653 , H01L29/66356 , H01L29/66659 , H01L29/7391
摘要： A method of manufacturing an I-MOS device includes forming a semiconductor layer (2) on a buried insulating layer (4). A gate structure (23) including a gate stack (14) is formed on the semiconductor layer, and used to (5) self align the formation of a source region (28) by implantation. Then, an etch step is used to selectively etch the gate structure (23) and this is followed by forming a drain region (36) by implantation. The method can precisely control the i-region length (38) between source region (28) and gate stack (14).

20. 发明授权

EP1844498B1 METHOD OF FABRICATING A DUAL-GATE FET 有权
标题翻译：用于生产双栅FET
公开(公告)号：EP1844498B1
公开(公告)日：2012-03-14
申请号：EP06710721.9
申请日：2006-01-23
申请人： NXP B.V.
发明人： VAN NOORT, Wibo, D. , WIDDERSHOVEN, Franciscus, P. , SURDEANU, Radu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L21/336 , H01L29/786 , H01L29/49 , H01L29/165
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7854
摘要： The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semiconductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short- length asymmetric dual-gate FET with two gate electrodes that can be biased separately.

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