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91. 发明授权

EP0312672B1 Offset correction circuit for a sigma-delta coding device 失效
标题翻译：用于SIGMA-DELTA编码设备的偏移校正电路
公开(公告)号：EP0312672B1
公开(公告)日：1992-07-22
申请号：EP87480015.4
申请日：1987-10-19
申请人： International Business Machines Corporation
发明人： Cukier, Maurice , Marciano, Frédérik , Michel, Patrick
IPC分类号： H03M1/60 , H04B14/06
CPC分类号： H04B14/062 , H03M3/356 , H03M3/50

92. 发明公开

EP0461721A1 Transmitter comprising an electronic arrangement for generating a modulated carrier signal 失效
标题翻译：发射机包括用于产生调制的载波信号的电子装置。
公开(公告)号：EP0461721A1
公开(公告)日：1991-12-18
申请号：EP91201429.7
申请日：1991-06-11
申请人： Philips Electronics N.V.
发明人： Voorman, Johannes Otto
IPC分类号： H04B14/06 , H04L27/06 , H04L27/04 , H04L27/20
CPC分类号： H04L27/04 , H04B14/06
摘要： Transmitter comprising an electronic arrangement for generating a modulated carrier signal, this arrangement comprising at least an adder included in a closed signal loop, a low-pass filter and a pulse shaper driven with a specific sample rate and constituted by a sigma-delta (one-bit) signal converter which includes a mixer driven with the carrier frequency fc so that the output signal of the pulse shaper is applied to the mixer and the frequency fc is equal to that or an integer multiple of the half sample rate.
摘要翻译：发射机，用于产生调制的载波信号，其包括电子装置的，该布置至少包括给加法器包括在一个封闭的信号循环中，一个低通滤波器和与特定采样速率驱动，并构成由Σ-Δ的脉冲整形器（一个位）信号转换器，其包括与载波频率fc驱动的混合器所以没有脉冲整形器的输出信号被施加到所述混频器和所述频率fc等于或没有帮助的整数倍的提醒样品。

93. 发明公开

EP0441980A1 TIME-DIVISION MULTIPLEX DATA RELAY EXCHANGE SYSTEM 失效
标题翻译：相关信息FÜRZEITMULTIPLEXDATEN。
公开(公告)号：EP0441980A1
公开(公告)日：1991-08-21
申请号：EP90912957.9
申请日：1990-09-04
申请人： FUJITSU LIMITED
发明人： TOMITA, Yoshihiro , FUJIWARA, Tatsuo , SHIMIZU, Hirotoshi , MATSUMOTO, Masashi , FUJIOKA, Yasushi
IPC分类号： H04M7/00 , H04B14/04 , H04B14/06 , H04J3/12 , H04Q11/04
CPC分类号： H04B14/068 , H04J3/12 , H04Q11/04
摘要： A relay exchange system in which a plurality of switchboards for switching transmission information contained in frames each consisting of m bits are connected in cascade using a plurality of transmission paths. a pair of multiplexers are provided at both ends of each of the transmission paths, frames each consisting of n (n
摘要翻译：多个交换机用于切换包含在帧中的传输信息，每个由m位组成的传输信息使用多个传输路径级联连接，在每个传输路径的两端提供一对多路复用器，每个由n组成的帧（n小于m）个比特，并且每个由包含（n-1）比特的特定帧组成的传输信息包括一个时隙形式的一比特的信令信息通过传输路径传输，并且交换机改造再次以外槽形式接收信令信息。每个特定帧包括用于标识指示其中插入信令信息的帧的相位的信令的信息。信令信息总是插入在多路复用器对之间以及交换机的输入和输出端口之间传输的特定帧中，并且总是基于识别信息来检测特定的帧。

94. 发明公开

EP0394493A1 AUDIO SIGNAL DEMODULATION CIRCUIT 失效
标题翻译： DEMODULATORSCHALTUNGFÜRSTIMMENSIGNALE。
公开(公告)号：EP0394493A1
公开(公告)日：1990-10-31
申请号：EP89911616.4
申请日：1989-10-24
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , NIPPON HOSO KYOKAI
发明人： MIYOSHI, Toshihiro , OKUMURA, Naoji , ARITA, Hisashi , ISHIKAWA, Kenji , NINOMIYA, Yuichi , OTSUKA, Yoshimichi , KAWASHIMA, Tadashi , IWAMOTO, Takushi
IPC分类号： H04B14/04 , H04B14/06
CPC分类号： H04N7/088 , H04B14/046
摘要： A circuit for demodulating digital voice signals to suppress the broken noise that generates when the synchronism is no more maintained or when the mute is forcibly applied. The demodulation circuit comprises a synchronism detecting circuit (18) and a muting circuit (17) which mutes the output of an interpolation circuit (16) responsive to a synchronizing lock signal produced from the synchronism detecting circuit (18) when the synchronism is no more maintained. The output of the interpolation circuit (16) that is a differential signal is muted and is then integrated to produce a voice signal of high sound quality without noise even when synchronism is not maintained.
摘要翻译：当不再保持同步时，内插电路（16）的输出响应同步锁定信号（18）而静音（17）。作为差分信号的内插电路（16）的输出被静音，然后被积分，以产生高音质的语音信号。

95. 发明公开

EP0384544A3 Analog-to-digital encoder and digital-to-analog decoder 失效
标题翻译：模拟数字编码器和数字到模拟解码器
公开(公告)号：EP0384544A3
公开(公告)日：1990-09-12
申请号：EP90200455.5
申请日：1984-10-08
申请人： DOLBY LABORATORIES LICENSING CORPORATION
发明人： Todd, Craig C. , Gundry, Kenneth James
IPC分类号： H04B14/06 , H04B1/62
CPC分类号： H03G9/005 , H03G5/16 , H03G9/025 , H03M3/022 , H04B1/62 , H04B14/064
摘要： In the encoder an audio input signal is firstly given an adaptive pre-emphasis characteristic by a pre-processing circuit (16) and is then converted to a digital signal for transmission by a delta-modulator (22). In order to minimise the digital bit rate the delta-modulator (22) is rendered adaptive by deriving a step-size control signal in a circuit (18) responsive to the slope of the input signal, and applying the control signal to vary the step size of the delta modulator (22). The bandwidth of the control signal is limited to say 50 Hz by the step-size circuit (18) itself or a subsequent low pass filter (24) in order to render the encoder insensitive to random step-size errors. The slow response of the control signal is compensated for by a delay circuit 20 preceding the delta-modulator (22). The corresponding decoder comprises an adaptive delta-demodulator and a circuit complementary to the pre-processing circuit (16). In order to keep the decoder as simple as possible it has no step-size derivation circuit. Instead, the step-size control signal is transmitted in conjunction with the main digital signal by way of an analog to digital converter (26). In the encoder a complementary digital to analog converter is followed by another bandwidth limiting filter to reduce the effect of transmission bit errors. The slow response of the decoder control signal is compensated for by transmitting the step-size information from the encoder with a time advance relative to the main digital signal.
摘要翻译：在编码器中，音频输入信号首先由预处理电路（16）给出自适应预加重特性，然后被转换成数字信号，以由增量调制器（22）传输。为了使数字比特率最小化，增量调制器（22）通过响应于输入信号的斜率导出电路（18）中的步长控制信号而变为自适应，并且施加控制信号以改变步骤 Δ调制器（22）的尺寸。控制信号的带宽由步进电路（18）本身或随后的低通滤波器（24）限制为50Hz，以使编码器对随机步长误差不敏感。控制信号的缓慢响应由在delta调制器（22）之前的延迟电路（20）补偿。相应的解码器包括自适应增量调制器和与预处理电路（16）互补的电路。为了使解码器尽可能简单，它没有步长推导电路。相反，步进大小控制信号通过模数转换器（26）与主数字信号一起发送。在编码器中，互补数模转换器之后是另一个带宽限制滤波器，以减少传输位错误的影响。解码器控制信号的缓慢响应通过以相对于主数字信号的时间提前从编码器发送步长信号来补偿。

96. 发明公开

EP0384544A2 Analog-to-digital encoder and digital-to-analog decoder 失效
标题翻译： Analog-Digital-Kodierer和Digital-Analog-Dekodierer。
公开(公告)号：EP0384544A2
公开(公告)日：1990-08-29
申请号：EP90200455.5
申请日：1984-10-08
申请人： DOLBY LABORATORIES LICENSING CORPORATION
发明人： Todd, Craig C. , Gundry, Kenneth James
IPC分类号： H04B14/06 , H04B1/62
CPC分类号： H03G9/005 , H03G5/16 , H03G9/025 , H03M3/022 , H04B1/62 , H04B14/064
摘要： In the encoder an audio input signal is firstly given an adaptive pre-emphasis characteristic by a pre-processing circuit (16) and is then converted to a digital signal for transmission by a delta-modulator (22). In order to minimise the digital bit rate the delta-modulator (22) is rendered adaptive by deriving a step-size control signal in a circuit (18) responsive to the slope of the input signal, and applying the control signal to vary the step size of the delta modulator (22). The bandwidth of the control signal is limited to say 50 Hz by the step-size circuit (18) itself or a subsequent low pass filter (24) in order to render the encoder insensitive to random step-size errors. The slow response of the control signal is compensated for by a delay circuit 20 preceding the delta-modulator (22). The corresponding decoder comprises an adaptive delta-demodulator and a circuit complementary to the pre-processing circuit (16). In order to keep the decoder as simple as possible it has no step-size derivation circuit. Instead, the step-size control signal is transmitted in conjunction with the main digital signal by way of an analog to digital converter (26). In the encoder a complementary digital to analog converter is followed by another bandwidth limiting filter to reduce the effect of transmission bit errors. The slow response of the decoder control signal is compensated for by transmitting the step-size information from the encoder with a time advance relative to the main digital signal.
摘要翻译：在编码器中，首先通过预处理电路（16）给音频输入信号赋予自适应预加重特性，然后将其转换为数字信号，以由Δ调制器（22）传输。为了使数字比特率最小化，增量调制器（22）通过响应于输入信号的斜率导出电路（18）中的步长控制信号而变为自适应，并且施加控制信号以改变步骤 Δ调制器（22）的尺寸。为了使编码器对随机步长误差不敏感，控制信号的带宽被步进电路本身或随后的低通滤波器（24）限制为50Hz。控制信号的缓慢响应由在delta调制器（22）之前的延迟电路（20）补偿。相应的解码器包括自适应增量调制器和与预处理电路（16）互补的电路。为了使解码器尽可能简单，它没有步长推导电路。相反，步进大小控制信号通过模数转换器（26）与主数字信号一起发送。在编码器中，互补数模转换器之后是另一个带宽限制滤波器，以减少传输位错误的影响。解码器控制信号的缓慢响应是通过以相对于主数字信号的时间提前从编码器发送步长信号来补偿的。

97. 发明公开

EP0376933A2 Digital to analog decoder 失效
标题翻译：数字 - 模拟 - Dekodierer。
公开(公告)号：EP0376933A2
公开(公告)日：1990-07-04
申请号：EP90200454.8
申请日：1984-10-08
申请人： DOLBY LABORATORIES LICENSING CORPORATION
发明人： Todd, Craig C. , Gundry, Kenneth James
IPC分类号： H04B14/06 , H04B1/62
CPC分类号： H03G9/005 , H03G5/16 , H03G9/025 , H03M3/022 , H04B1/62 , H04B14/064
摘要： A digital to analog decoder converts an input digital signal into an output analog signal and alters the spectral content of the output signal. An adaptive delta demodulator (42) converts the input digital signal into an analog signal to provide the output analog signal in accordance with a step-size control signal (28). Processing means (96) alter the spectral content of the output signal in accordance with a spectral control signal (82). The step-size and spectral control signals both have limited bandwidths (46, 80) so that substantially the same output signal is obtained irrespective of the order in which the delta demodulation (42) and altering of the spectral content (96) are performed.
摘要翻译：数字到模拟解码器将输入数字信号转换为输出模拟信号并改变输出信号的频谱含量。自适应增量解调器（42）将输入的数字信号转换为模拟信号，以根据步长控制信号（28）提供输出模拟信号。处理装置（96）根据频谱控制信号（82）改变输出信号的频谱含量。步长和频谱控制信号都具有有限的带宽（46,80），使得获得基本上相同的输出信号，而不管执行增量解调（42）和改变频谱内容（96）的顺序。

98. 发明公开

EP0214235A4 ERROR DETECTION AND CONCEALMENT USING PREDICTED SIGNAL VALUES. 失效
标题翻译：检错和屏蔽装置信号预测。
公开(公告)号：EP0214235A4
公开(公告)日：1990-02-05
申请号：EP86901671
申请日：1986-02-21
申请人： SCIENTIFIC ATLANTA
发明人： LUCAS KEITH BEAUFORT HILLS ROA
IPC分类号： G11B20/18 , H03M13/00 , H04B14/04 , H04B14/06
CPC分类号： H03M13/00 , G11B20/1876

99. 发明公开

EP0240123A3 Digital encoder and decoder synchronization in the presence of data dropouts 失效
标题翻译：数字编码器中的数字编码器和解码器同步
公开(公告)号：EP0240123A3
公开(公告)日：1989-05-24
申请号：EP87301412.0
申请日：1987-02-19
申请人： AT&T Corp.
发明人： Tomasevich, George Richard
IPC分类号： H04B14/06
CPC分类号： H04B14/068
摘要： Recovery from transmission errors is facilitated by initializing state variables to prescribed values in both a digital encoder used in transmitting a signal and a corresponding digital decoder used in receiving the signal when the transmission channel becomes inactive. Additionally, the values of the encoder and decoder state variables are held constant (via 2706, 2709, 2710, 2711) for up to a prescribed interval upon the transmission channel becoming inactive. The state variables are held constant until either the prescribed holding interval elapses or the transmission channel becomes active. If the prescribed holding interval elapses before the transmission channel becomes active the state variables are initialized to the prescribed values (via 2711). However, if the encoder or decoder transmission channel becomes active before the prescribed holding interval has elapsed, the encoder or decoder, respectively, returns to its normal operative state (via 2709) and the state variables are allowed to adapt.
摘要翻译：来自接收接入模块的分组分解器的样本（I'（k））被提供给可变速率逆量化器（2702,2703）和量化器适配单元（2701），该量化器适配单元选择用于生成其比例因子的适当电路。当在特定时隙中不存在分组时，量化差分样本与来自自适应预测器（2705）的样本估计相加（2704,2707）以产生具有噪声信号（2714）的多路复用重构样本（2708）。在传输通道不活动的情况下，编码器和解码器状态变量（2706）在被初始化之前保持恒定的规定间隔（2711），除非在恢复时间限制内（2709）恢复正常自适应操作。

100. 发明授权

EP0080725B1 Verfahren und Anordnung zur A/D-Wandlung 失效
标题翻译：用于A / D转换的方法和装置
公开(公告)号：EP0080725B1
公开(公告)日：1988-03-09
申请号：EP82111015.2
申请日：1982-11-29
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Giancarlo, Charles
IPC分类号： H04B14/06 , H03M3/04
CPC分类号： H04B14/06
摘要： 1. A method of A/D-conversion, wherein the analogue input signal (5) is integrated, amplified and then quantised, and where the quantised signal is fed-back to the input signal, characterized in that the quantised signal (8) comprises n (n>1) quantisation stages and is digitally integrated by a periodic sum formation, that the digitally integrated, signal (9) comprises (N (N>n) bits, is converted into an analogue signal (6), and is fed-back to the input signal (5), and that the difference between the input signal (5) and the fed-back analogue signal (6) is integrated in analogue fashion and is amplified.
摘要翻译： 1.一种A / D转换的方法，其中模拟输入信号（5）被积分，放大和量化，并且其中量化的信号被反馈到输入信号，其特征在于量化信号（8）包括n（n> 1）量化级并且通过周期性和形成数字积分，数字积分的信号（9）包括（N（N> n）位，被转换成模拟信号（6），并且是反馈到输入信号（5），并且输入信号（5）和反馈模拟信号（6）之间的差异以模拟方式被积分并被放大。

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