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91. 发明公开

EP1399827A1 SYSTEM AND METHOD FOR DELAYING A STROBE SIGNAL 有权
标题翻译：系统和方法用于传输的频闪
公开(公告)号：EP1399827A1
公开(公告)日：2004-03-24
申请号：EP02731858.3
申请日：2002-05-16
申请人： INTEL CORPORATION
发明人： ZUMKEHR, John
IPC分类号： G06F13/16 , G11C7/22
CPC分类号： G11C7/04 , G06F13/1689 , G11C7/1072 , G11C7/1078 , G11C2207/107 , G11C2207/2254
摘要： A system, method and medium may delay a strobe signal based upon a delay base and a delay adjustment to reduce effects of process variations and/or environmental changes.

92. 发明公开

EP1397807A2 ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS 审中-公开
标题翻译：校准延迟元素具有高带宽内存异步组件
公开(公告)号：EP1397807A2
公开(公告)日：2004-03-17
申请号：EP02726564.4
申请日：2002-01-30
申请人： Rambus, Inc.
发明人： WARE, Frederick, A. , TSERN, Ely, K. , HAMPEL, Craig, E. , STARK, Donald, C.
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different synchronous delays and to strobe sequential pipeline elements of the memory device.

93. 发明公开

EP1324491A1 TIMER CIRCUIT AND SEMICONDUCTOR MEMORY INCORPORATING THE TIMER CIRCUIT 审中-公开
标题翻译： Z ALT ICH UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG
公开(公告)号：EP1324491A1
公开(公告)日：2003-07-02
申请号：EP01955569.7
申请日：2001-08-03
申请人： NEC Corporation
发明人： TAKAHASHI, Hiroyuki, NEC Corporation , SONODA, Masatoshi, NEC Corporation , NAKAGAWA, Atsushi, NEC Corporation
IPC分类号： H03K3/03 , G11C11/34
CPC分类号： H03K3/0315 , G11C7/04 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/40626 , G11C11/4074 , G11C11/4076 , H03K3/011
摘要： It is an object to provide a timer circuit which exhibits a tendency of decreasing a timer cycle upon a temperature increase and another tendency of increasing the timer cycle upon a temperature decrease. A diode D has a current characteristic depending upon temperature. A forward current flows through an n-type MOS transistor N1 which forms the primary side of a current mirror. Another current flowing through a p-type MOS transistor P2 and an n-type MOS transistor N3 which form the secondary side of the current mirror is defined depending upon the current flowing through the n-type MOS transistor N1. The current flowing through the p-type MOS transistor P2 and the n-type MOS transistor N3 is supplied as an operating current of a ring oscillator comprising inverters I1 ∼ I3. Accordingly, the cycle (timer cycle) of a clock signal CLK outputted from this ring oscillator reflects a temperature characteristic of the diode D, wherein the timer cycle decreases with increasing the temperature.
摘要翻译：本发明的目的是提供一种定时器电路，其在温度升高时呈现减小定时器周期的趋势，以及在温度降低时增加定时器周期的另一趋势。二极管D具有取决于温度的电流特性。正向电流流过形成电流镜的初级侧的n型MOS晶体管N1。形成电流镜的二次侧的p型MOS晶体管P2和n型MOS晶体管N3的另一个电流根据流经n型MOS晶体管N1的电流而定义。流过p型MOS晶体管P2和n型MOS晶体管N3的电流作为包括逆变器I1类似I3的环形振荡器的工作电流被提供。因此，从该环形振荡器输出的时钟信号CLK的周期（定时器周期）反映二极管D的温度特性，其中定时器周期随着温度的升高而降低。

94. 发明公开

EP1293984A2 Synchronous semiconductor memory device 有权
标题翻译：同步Halbleiterspeicheranordnung
公开(公告)号：EP1293984A2
公开(公告)日：2003-03-19
申请号：EP02020557.1
申请日：2002-09-17
申请人： Kabushiki Kaisha Toshiba
发明人： Kawaguchi, Kazuaki, Intellectual Property Division , Ohshima, Shigeo, Intellectual Property Division
IPC分类号： G11C7/10
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072
摘要： A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command (RDA) and a write operation of writing information into the memory cells according to a write command (WRA). The synchronous semiconductor memory device further has a command sensing circuit which senses whether a first command inputted in synchronization with an external clock signal (VCLK) is the read command (RDA) or the write command (WRA). The synchronous semiconductor memory device further has a bank timer circuit (11) which, when the command sensing circuit has sensed either the read command (RDA) or the write command (WRA), sets the end time of the restore operation of a row address strobe (RAS) and the start time of the precharge operation of the RAS according to the external clock signal (VCLK).
摘要翻译：同步半导体存储器件具有存储器部分，其包括具有多个存储器单元的存储器单元阵列，并且能够根据读取命令（RDA）和写入的写入操作从存储器单元读取信息的读取操作信息根据写命令（WRA）存入存储单元。同步半导体存储器件还具有命令检测电路，其检测与外部时钟信号（VCLK）同步输入的第一命令是读命令（RDA）还是写命令（WRA）。同步半导体存储器件还具有一个存储体定时器电路（11），当命令感测电路已经感测到读取命令（RDA）或写入命令（WRA）时，设置行地址的恢复操作的结束时间选通（RAS）和根据外部时钟信号（VCLK）的RAS的预充电操作的开始时间。

95. 发明公开

EP1058270A1 Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase 有权
标题翻译： Vorspannungsstufe zum Vorspannen des Drains einernichtflüchtigenSpeicherzellewährenddes Auslesens
公开(公告)号：EP1058270A1
公开(公告)日：2000-12-06
申请号：EP99830348.1
申请日：1999-06-04
申请人： STMicroelectronics S.r.l.
发明人： Micheloni, Rino
IPC分类号： G11C16/06
CPC分类号： G11C7/04 , G11C11/5621 , G11C11/5642 , G11C16/24 , G11C16/30
摘要： The read circuit (50) comprises a biasing stage (12) connected to the memory cell (6) to be read and having the purpose of biasing the drain terminal of the memory cell (6) at a preset operating potential, typically 1 V; and a regulating circuit (52) connected to a supply line (2) set at a supply voltage (V CC ) and supplying to the biasing stage (12) a bias current (Ip) which is stable as the temperature and the supply voltage (V CC ) vary.
摘要翻译：读取电路（50）包括连接到要读取的存储单元（6）的偏置级（12），其目的是将存储单元（6）的漏极端子以预定的操作电位（通常为1V）偏置; 以及调节电路（52），连接到设置在电源电压（VCC）的供电线（2），并向偏置级（12）提供作为温度和电源电压（VCC）稳定的偏置电流（Ip））不一样。

96. 发明授权

EP0774759B1 EEPROM having reference cells tracking charge leakage of memory cells 失效
标题翻译： EEPROM与以下参考单元的存储单元的电荷损失
公开(公告)号：EP0774759B1
公开(公告)日：1999-03-24
申请号：EP96114367.4
申请日：1990-04-12
申请人： SanDisk Corporation
发明人： Mehrotra,Sanjay, , Harari,Eliyahou,
IPC分类号： G11C16/06 , G11C11/56
CPC分类号： G11C11/5621 , G11C7/04 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5631 , G11C2211/5634 , G11C2211/5645

97. 发明公开

EP0539358A4 EP0539358A4 - 失效
标题翻译： EP0539358A4 - Google专利
公开(公告)号：EP0539358A4
公开(公告)日：1995-01-11
申请号：EP90906720
申请日：1990-04-12
IPC分类号： G11C16/02 , G01R31/28 , G11C7/00 , G11C11/00 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/34
CPC分类号： G11C11/5621 , G11C7/04 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5631 , G11C2211/5634 , G11C2211/5645
摘要： Improvements in the circuits and techniques for read, write and erase of EEprom memory (60). In the circuits for normal read, and read between write or erase for verification, the reading is made relative to set of threshold levels as provided by a corresponding set of reference cells (431, 432 etc.) which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells (529) also exists for the whole memory chip acting as a master reference.
摘要翻译： EEprom存储器（60）的电路和读取，写入和擦除技术的改进。在用于正常读取和在用于验证的写入或擦除之间进行读取的电路中，读取是相对于由相应的一组参考单元（431,432等）提供的阈值水平的集合进行的，所述参考单元紧密跟踪并调整存储单元所呈现的变化。在一个实施例中，存储器单元的每个闪存扇区具有其自己的用于读取该扇区中的单元的参考单元，并且对于充当主参考的整个存储器芯片也存在一组参考单元（529）。

98. 发明授权

EP4116974B1 ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM) 有权
公开(公告)号：EP4116974B1
公开(公告)日：2024-08-28
申请号：EP22182464.2
申请日：2022-07-01
IPC分类号： G11C5/00 , G11C7/04 , G11C11/412 , G11C11/419 , G11C7/10
CPC分类号： G11C11/412 , G11C11/4125 , G11C11/419 , G11C5/005 , G11C7/04 , G11C7/1006

99. 发明授权

EP4080508B1 MEMORY 有权
公开(公告)号：EP4080508B1
公开(公告)日：2024-08-28
申请号：EP21857322.8
申请日：2021-06-18
IPC分类号： G11C5/06 , G11C5/02 , G11C5/14 , G11C11/4096 , G11C11/4097 , G11C7/04 , G11C7/10 , G11C7/18 , H10B12/00
CPC分类号： G11C5/025 , G11C5/063 , G11C11/4097 , H10B12/482 , H10B12/50 , G11C7/18 , G11C5/14 , G11C7/1069 , G11C7/1096 , G11C7/04 , G11C11/4096 , H01L27/0207 , H10B12/00

100. 发明授权

EP4095857B1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：EP4095857B1
公开(公告)日：2024-07-17
申请号：EP20945120.2
申请日：2020-12-15
IPC分类号： G11C7/04 , G11C29/02 , H01L25/18
CPC分类号： G11C7/04 , G11C29/028 , H01L25/18 , G11C29/02

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