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91. 发明公开

EP0982660A2 Multiprocessor system with plurality of nodes 审中-公开
标题翻译： Multiprozessorsystem mit mehreren Knoten
公开(公告)号：EP0982660A2
公开(公告)日：2000-03-01
申请号：EP99116639.8
申请日：1999-08-25
申请人： Hitachi, Ltd.
发明人： Tarui, Toshiaki , Okochi, Toshio , Fujii, Hiroaki , Yasuda, Yoshiko , Inohara, Shigekazu
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F2212/2542
摘要： A NUMA type multiprocessor including a shared memory dispersedly arranged in a plurality of nodes, wherein each node includes a register for instructing a page for initialization and a register for giving an instruction to invalidate the data on the caches of other nodes for each page when an OS recovers the page. Means is disposed for restricting line transfer from other nodes and invalidating the data on the caches of other nodes when write occurs to the page designated by the former for initialization, etc. A command for collectively invalidating the page to other nodes is generated for the page designated by the latter. There are further disposed means for storing the state where the page is exclusive, in response to each page of the main memory inside the node, and means for setting the state of the corresponding page to the exclusive state when the execution of the latter command is completed.
摘要翻译：包括分散布置在多个节点中的共享存储器的NUMA型多处理器，其中每个节点包括用于指示页面进行初始化的寄存器和用于给出每个页面的其他节点的高速缓存上的数据的指令的寄存器，当一个操作系统恢复页面。为了限制从其他节点的线路传输而设置的装置，并且当由前者指定用于初始化的页面发生写入等时，使其他节点的高速缓存上的数据无效。为了页面生成用于将页面合并使其他节点的命令由后者指定。还有一种装置，用于存储响应于节点内的主存储器的每一页的页面是排他的状态，以及用于当后一个命令的执行是相应页面的执行时将相应页面的状态设置为独占状态的装置完成。

92. 发明公开

EP0817080A2 Multi-level cache memory 失效
标题翻译： Mehrstufiger Cachespeicher
公开(公告)号：EP0817080A2
公开(公告)日：1998-01-07
申请号：EP97304726.9
申请日：1997-06-30
申请人： SUN MICROSYSTEMS, INC.
发明人： Hagersten, Erik E. , Hill, Mark D.
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0888 , G06F2212/2542 , G06F2212/272
摘要： An efficient scheme for selecting memory storage modes of a multi-level cache hierarchy of a computing system having at least a lower-level cache (LLC) and a higher-level cache (HLC). In one embodiment, memory space in the lower-level cache (LLC) is allocated in cache-line sized units, while memory space in the higher-level cache (HLC) is allocated in page sized units; with each page including two or more cache lines. Accordingly, during the execution of a program. cache-line-sized components of a page-sized block of data are incrementally stored in the cache lines of the LLCs. Subsequently, the system determines that it is time to review the allocation of cache resources, i.e., between the LLC and the HLC. The review trigger may be external to the processor, e.g., a timer interrupting the processor on a periodic basis. Alternatively, the review trigger may be from the LLC or the HLC, e.g., when the LLC is full, or when usage of the HLC drops below a certain percentage. A review of the allocation involves identifying components associated with their respective blocks of data and determining if the number of cached components identified with the blocks exceed a threshold. If the threshold is exceeded for cached components associated with a particular block, space is allocated in the HLC for storing components from the block. This scheme advantageously increases the likelihood of future cache hits by optimally using the HLC to store blocks of memory with a substantial number of useful components.
摘要翻译：一种用于选择具有至少下级高速缓存（LLC）和更高级高速缓存（HLC）的计算系统的多级高速缓存层级的存储器存储模式的有效方案。在一个实施例中，低级缓存（LLC）中的存储器空间被分配在高速缓存行大小的单元中，而较高级高速缓存（HLC）中的存储器空间被分配为页大小的单元; 每个页面包括两个或多个缓存行。因此，在执行程序期间。页面大小的数据块的高速缓存行大小的组件被递增地存储在LLC的高速缓存行中。随后，系统确定是时候审查缓存资源的分配，即LLC和HLC之间的分配。审查触发可以在处理器外部，例如定时器周期性地中断处理器。或者，审查触发可以来自LLC或HLC，例如当LLC已满时，或者当HLC的使用降低到特定百分比以下时。对分配的审查包括识别与其相应数据块相关联的组件，并确定用块识别的高速缓存组件的数量是否超过阈值。如果超过与特定块相关联的缓存组件的阈值，则在HLC中分配空间以从块中存储组件。该方案有利地通过最佳地使用HLC来存储具有相当数量的有用组件的存储块来增加未来高速缓存命中的可能性。

93. 发明公开

EP0817076A1 A multiprocessing computer system employing local and global address spaces and multiple access modes 失效
标题翻译：多处理器计算机系统与本地和全局地址空间和多种接入方式
公开(公告)号：EP0817076A1
公开(公告)日：1998-01-07
申请号：EP97304652.7
申请日：1997-06-27
申请人： SUN MICROSYSTEMS, INC.
发明人： Hagerstein, Erik E. , Loewenstein, Paul N.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0284 , G06F12/0813 , G06F2212/2542 , G06F2212/272
摘要： A multiprocessing computer system employing local and global address spaces and multiple access modes. A processor within a node may initiate a transaction which requires inter-node communication. A local address may be translated to a global address. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node to the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.
摘要翻译：多处理计算机系统聘用本地和全局地址空间和多种接入方式。一个节点内的处理器可以启动需要哪些节点间通信的事务。本地地址可以被转换为全局地址。当一个请求由请求节点到归属节点发送，归属节点发送读取和/或无效的要求，以保持所要求的数据的高速缓存的副本的任何从属节点。从主节点到从节点的需求可以各自有利地包括指示该请求代理shoulderstand期望接收的回复数的值。奴隶们回信请求节点与数据或确认。每个答复还可以包括答复请求shoulderstand预期的数量。当接收到所有预期的答复，请求节点可以发送一个完成消息回到了家中，并已完成可处理交易，并与后续处理进行。

94. 发明公开

EP0817070A1 Multiprocessing system employing a coherency protocol including a reply count 失效
标题翻译： Mehrrechnersystem mit einem die Anzahl der Antworten enthaltendenKohärenzprotokoll
公开(公告)号：EP0817070A1
公开(公告)日：1998-01-07
申请号：EP97304600.6
申请日：1997-06-27
申请人： SUN MICROSYSTEMS, INC.
发明人： Hagersten, Erik E. , Loewenstein, Paul N.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0813 , G06F2212/2542
摘要： A multiprocessing computer system employing a three-hop communications protocol including a reply count communication. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node to the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.
摘要翻译：一种采用包括应答计数通信的三跳通信协议的多处理计算机系统。当请求节点向家庭节点发送请求时，家庭节点向保持所请求数据的缓存副本的任何从节点发送读取和/或无效请求。从家庭节点到从节点的需求可以各自有利地包括指示请求代理人应该期望接收的应答数量的值。从机通过数据或确认回复到请求节点。每个答复还可以包括请求者应该期望的答复数。在接收到所有预期的答复之后，请求节点可以将完成消息发送回家并且可以将该事务处理为已完成并继续进行后续处理。

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