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1. 发明授权

EP0892409B1 Semiconductor memory device 失效
公开(公告)号：EP0892409B1
公开(公告)日：2004-04-28
申请号：EP98305701.9
申请日：1998-07-16
申请人： TEXAS INSTRUMENTS INCORPORATED , Hitachi, Ltd.
发明人： Hira, Masayuki , Sukegawa, Shunichi , Bessho, Shinji , Takahashi, Yasushi , Arai, Koji , Takahashi, Tsutomu , Takahashi, Tsugio
IPC分类号： G11C11/409 , G11C7/06
CPC分类号： G11C7/065 , G11C11/4091

2. 发明公开

EP0915475A2 Semiconductor memory 有权
标题翻译： Halbleiterspeicher
公开(公告)号：EP0915475A2
公开(公告)日：1999-05-12
申请号：EP98203781.4
申请日：1998-11-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hira, Masayuki , Sukegawa, Shunichi , Bessho, Shinji , Takahashi, Yasushi , Arai, Koji , Takahashi, Tsutomu
IPC分类号： G11C5/14 , G11C7/06 , G11C5/06
CPC分类号： G11C5/063 , G11C5/143 , G11C5/147 , G11C7/06
摘要： In a memory operating according to the over-drive system a drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG0 is connected to the V DL line which raises the V DL line to a voltage higher than V DL beforehand prior to changing to internal power supply voltage V DL from external power supply voltage V DD , and restores the V DL line voltage which drops after the change to V DL . More specifically, there are detecting circuit part 40 which detects the V DL line potential, first switching element M1 connected between the V DL line and the V DD line and which operates according to the detected result of detecting circuit part 40, and second switching element M2 connected between common voltage V SS and connection node ND1 between first switching element M1 and detecting circuit part 40, which changes the potential of connection node ND1 by conducting according to input preliminary voltage step up signal MVDL, and by it conducts first switching element M1 for a fixed time.
摘要翻译：在根据过驱动系统操作的存储器中，从过驱动系统的外部电源电压改变内部电源电压的电力时，可以大幅度地抑制在变化之后的电源电平的下降。电压产生电路VG0连接到VDL线，VDL线在从外部电源电压VDD变为内部电源电压VDL之前事先将VDL线升高到高于VDL的电压，并且将更改后的VDL线电压恢复到 VDL。更具体地，存在检测VDL线电位的检测电路部40，连接在VDL线与VDD线之间的第一开关元件M1，其根据检测电路部40的检测结果进行动作，第二开关元件M2连接在第一开关元件M1和检测电路部分40之间的公共电压VSS和连接节点ND1，其通过根据输入的初步升压信号MVDL进行导通而改变连接节点ND1的电位，并且通过其将第一开关元件M1导通固定时间。

3. 发明授权

EP0915475B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：EP0915475B1
公开(公告)日：2010-01-13
申请号：EP98203781.4
申请日：1998-11-10
申请人： Texas Instruments Incorporated
发明人： Hira, Masayuki , Sukegawa, Shunichi , Bessho, Shinji , Takahashi, Yasushi , Arai, Koji , Takahashi, Tsutomu
IPC分类号： G11C5/14 , G11C7/06 , G11C5/06
CPC分类号： G11C5/063 , G11C5/143 , G11C5/147 , G11C7/06

4. 发明公开

EP0915475A3 Semiconductor memory 有权
标题翻译：半导体内存
公开(公告)号：EP0915475A3
公开(公告)日：2000-01-26
申请号：EP98203781.4
申请日：1998-11-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hira, Masayuki , Sukegawa, Shunichi , Bessho, Shinji , Takahashi, Yasushi , Arai, Koji , Takahashi, Tsutomu
IPC分类号： G11C5/14 , G11C7/06 , G11C5/06
CPC分类号： G11C5/063 , G11C5/143 , G11C5/147 , G11C7/06
摘要： In a memory operating according to the over-drive system a drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG0 is connected to the V DL line which raises the V DL line to a voltage higher than V DL beforehand prior to changing to internal power supply voltage V DL from external power supply voltage V DD , and restores the V DL line voltage which drops after the change to V DL . More specifically, there are detecting circuit part 40 which detects the V DL line potential, first switching element M1 connected between the V DL line and the V DD line and which operates according to the detected result of detecting circuit part 40, and second switching element M2 connected between common voltage V SS and connection node ND1 between first switching element M1 and detecting circuit part 40, which changes the potential of connection node ND1 by conducting according to input preliminary voltage step up signal MVDL, and by it conducts first switching element M1 for a fixed time.
摘要翻译：在根据过驱动系统操作的存储器中，当从过驱动系统的外部电源电压改变到内部电源电压的功率时，刚刚改变之后的电源电平的下降可以被大大地抑制。电压生成电路VG0连接到VDL线，其在从外部电源电压VDD改变到内部电源电压VDL之前预先将VDL线升高到高于VDL的电压，并且将改变之后降低的VDL线电压恢复到 VDL。更具体地说，有检测VDL线电位的检测电路部分40，连接在VDL线和VDD线之间并根据检测电路部分40的检测结果工作的第一开关元件M1，以及连接在VDL线和VDD线之间的第二开关元件M2 公共电压VSS以及第一开关元件M1和检测电路部分40之间的连接节点ND1，其通过根据输入初步升压信号MVDL进行导通来改变连接节点ND1的电位，并且通过它将第一开关元件M1导通固定时间。

5. 发明公开

EP0892409A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0892409A3
公开(公告)日：1999-07-28
申请号：EP98305701.9
申请日：1998-07-16
申请人： TEXAS INSTRUMENTS INCORPORATED , Hitachi, Ltd.
发明人： Hira, Masayuki , Sukegawa, Shunichi , Bessho, Shinji , Takahashi, Yasushi , Arai, Koji , Takahashi, Tsutomu , Takahashi, Tsugio
IPC分类号： G11C11/409 , G11C7/06
CPC分类号： G11C7/065 , G11C11/4091
摘要： Controlling the timing for the overdrive of the sense amplifiers in response to the conductor length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines. The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the conductor length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the conductor between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.
摘要翻译：响应于读出放大器与电源电压供应节点之间的导体长度来控制读出放大器的过驱动的定时，并且通过防止位线的过度过驱动来设计功耗的降低。根据用于驱动读出放大器的电源的供电节点CT0，CT1，CT2之间的导体长度和每个读出放大器组SB0至SB16之间的导体长度来控制到每个读出放大器组的电源电压的供应定时，并且由于到近端的读出放大器组SB0的过驱动电压的供给时间被设定得短，并且过驱动电压的供给时间随着朝向远端而被连续设定得更长，所以感测延迟源于电压补偿在供电节点和读出放大器组之间的导体中产生的压降，可以实现远端和近端的位线的过驱动的均匀性，读出放大器组（存储单元垫）可以避免，并且进一步地，可以实现功耗的降低。

6. 发明公开

EP0892409A2 Semiconductor memory device 失效
公开(公告)号：EP0892409A2
公开(公告)日：1999-01-20
申请号：EP98305701.9
申请日：1998-07-16
申请人： TEXAS INSTRUMENTS INCORPORATED , Hitachi, Ltd.
发明人： Hira, Masayuki , Sukegawa, Shunichi , Bessho, Shinji , Takahashi, Yasushi , Arai, Koji , Takahashi, Tsutomu , Takahashi, Tsugio
IPC分类号： G11C11/409 , G11C7/06
CPC分类号： G11C7/065 , G11C11/4091
摘要： Controlling the timing for the overdrive of the sense amplifiers in response to the conductor length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.
The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the conductor length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the conductor between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

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