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1. 发明公开

EP2615546A4 METHOD AND SYSTEM, SCHEDULER FOR PARALLEL SIMULATING PROCESSORS 审中-公开
标题翻译： VERFAHREN UND SYSTEM SOWIE PLANERFÜRPARALLELE SIMULATIONSPROZESSOREN
公开(公告)号：EP2615546A4
公开(公告)日：2013-12-11
申请号：EP12828153
申请日：2012-08-27
申请人： HUAWEI TECH CO LTD
发明人： YE HANDONG , CAO JIONG , YE XIAOCHUN , WANG DA
IPC分类号： G06F9/455 , G06F11/26
CPC分类号： G06F17/5022 , G06F11/261
摘要： The present invention provides a method, system, and scheduler for simulating multiple processors in parallel. The scheduler create one or more slave threads using a master thread, and determines a processor that is simulated by the master thread and a processor that is simulated by a slave thread, so that the scheduler is capable of using the master thread and the one or more slave threads to invoke, through a first execute interface, the determined processor that is simulated by the master thread and the determined processor that is simulated by the slave thread to execute a corresponding instruction, where the first execute interface is registered with the scheduler by the determined processor that is simulated by the master thread and the determined processor that is simulated by the slave thread. Because the master thread and the one or more slave threads are able to be used to schedule a processor that is simulated by the master thread and a processor that is simulated by a slave thread each time, multiple processors are able to be simulated in parallel. This avoids a problem in the prior art that multiple processors cannot be simulated in parallel because only one processor is scheduled each time, thereby increasing simulation efficiency; meanwhile, processor resources of a host where the scheduler is located are able to be fully utilized, thereby improving resource utilization.
摘要翻译：本发明提供了并行模拟多个处理器的方法，系统和调度器。调度器使用主线程创建一个或多个从线程，并且确定由主线程模拟的处理器和由从线程模拟的处理器，使得调度器能够使用主线程，更多的从线程通过第一执行接口调用由主线程和由从线程模拟的确定的处理器来执行相应指令的确定的处理器，其中第一执行接口通过以下方式向调度器注册：由主线程和由从线程模拟的确定的处理器所模拟的确定的处理器。因为主线程和一个或多个从线程能够用于调度由主线程模拟的处理器和每次由从线程模拟的处理器，所以能够并行地模拟多个处理器。这避免了现有技术中由于每次调度一个处理器而不能并行地模拟多个处理器的问题，从而提高了仿真效率; 同时，能够充分利用调度器所在主机的处理器资源，从而提高资源利用率。

2. 发明公开

EP2770429A4 METHOD AND DEVICE FOR GENERATING SIMULATOR 有权
标题翻译：产生模拟器的方法和装置
公开(公告)号：EP2770429A4
公开(公告)日：2014-10-08
申请号：EP12850194
申请日：2012-11-19
申请人： HUAWEI TECH CO LTD
发明人： YE HANDONG , ZHAO PENG , ZHENG SENHUO , CAO JIONG
IPC分类号： G06F9/455 , G06F9/44 , G06F9/45 , G06F17/50
CPC分类号： G06F9/455 , G06F8/30 , G06F8/53 , G06F9/4552 , G06F17/5022 , G06F2217/86
摘要： The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The simulator generation method includes: obtaining an instruction set configuration file; generating a decoding table and a decoding algorithm according to the instruction set configuration file, where the decoding table includes: an instruction code table, an instruction description table, and a bit field table, and assembly instruction operation code is recorded in the instruction code table, detailed information of each piece of the assembly instruction operation code in recorded in the instruction description table, and a method for calculating a numerical value in each operand bit field is recorded in the bit field table; and generating a simulator according to the decoding table, the decoding algorithm, and module code, where the module code is code used to simulate an action of an assembly instruction and code of a non-decoding algorithm in a decoding process. The solutions in the present invention are applicable to simulator generation.
摘要翻译：本发明公开了一种与模拟器生成领域相关的模拟器生成方法和装置，其用于实现模拟器的快速便携性和高效率。所述模拟器生成方法包括：获取指令集配置文件; 根据指令集配置文件生成解码表和解码算法，其中解码表包括：指令代码表，指令描述表和位字段表，并且汇编指令操作码被记录在指令代码表中记录在指令说明表中的每个装配指令操作代码的详细信息和用于计算每个操作数位字段中的数值的方法被记录在位字段表中; 以及根据解码表，解码算法和模块代码生成模拟器，其中模块代码是用于在解码过程中模拟汇编指令的动作和非解码算法的代码的代码。本发明的解决方案适用于模拟器生成。

3. 发明公开

EP2672388A4 MULTI-PROCESSOR PARALLEL SIMULATION METHOD, SYSTEM AND SCHEDULER 有权
标题翻译：平行机多模式仿真系统
公开(公告)号：EP2672388A4
公开(公告)日：2014-08-20
申请号：EP12832221
申请日：2012-09-13
申请人： HUAWEI TECH CO LTD
发明人： YE HANDONG , CAO JIONG , YE XIAOCHUN , WANG DA
IPC分类号： G06F11/26
CPC分类号： G06F17/5022 , G06F11/261
摘要： The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.
摘要翻译：本发明提供并行模拟多个处理器的方法和系统以及调度器。在该实施例中，调度器将需要调试的待仿真处理器的调试接口信息映射到多个处理器的并行仿真期间调度器，使得调度器能够通过使用主线程来调试待编程的，模拟处理器需要通过待仿真处理器的调试接口进行调试，需要调试接口信息指示的调试，从而在多个处理器的并行仿真期间实现调试。

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