专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1995001021A1 NRZ CLOCK RECOVERY WITH INSTANT LOCK 审中-公开
标题翻译： NRZ时钟恢复与即时锁定
公开(公告)号：WO1995001021A1
公开(公告)日：1995-01-05
申请号：PCT/US1994007001
申请日：1994-06-23
申请人： XIRCOM, INCORPORATED
发明人： XIRCOM, INCORPORATED , VASUDEVAN, Swaminatha, V.
IPC分类号： H04L07/02
CPC分类号： H04L7/0331
摘要： A modeless digital non-return to zero (NRZ) clock recovery circuit uses a high speed clock signal to oversample incoming digital data and divide each bit cell into a number of subcells. When a data transition occurs in the input data, logic in the circuit (20) determines whether the transition has occurred in an appropriate time window. If the data transition is several subcells out of alignment, a larger modification is made to align the output clock signal to the data transition. In any case, the clock adjustment occurs within one clock cycle of the high speed clock signal. The circuit includes a counter (24) with parallel enable, and combinatorial logic (28) determines the next counter state. The counter (24) is loaded with the correct state value on every detected edge transition of the input data stream. Logic synchronizes the incoming data stream and high speed clock, and synthesizes the output clock signal from the counter state information.
摘要翻译：无模式数字不归零（NRZ）时钟恢复电路使用高速时钟信号对输入数字数据进行过采样，并将每个位单元划分成多个子单元。当在输入数据中发生数据转换时，电路（20）中的逻辑确定在适当的时间窗口中是否发生转换。如果数据转换是不对齐的几个子单元，则进行较大的修改以将输出时钟信号与数据转换对齐。在任何情况下，时钟调整发生在高速时钟信号的一个时钟周期内。电路包括具有并联使能的计数器（24），组合逻辑（28）确定下一个计数器状态。计数器（24）在输入数据流的每个检测到的边沿转换上加载正确的状态值。逻辑同步输入数据流和高速时钟，并从计数器状态信息合成输出时钟信号。

2. 发明申请

WO1988007294A1 PROCESS AND CIRCUITRY FOR TIMING SYNCHRONIZATION 审中-公开
标题翻译：用于同步同步的过程和电路
公开(公告)号：WO1988007294A1
公开(公告)日：1988-09-22
申请号：PCT/DE1988000019
申请日：1988-01-16
申请人： ANT NACHRICHTENTECHNIK GMBH , HESPELT, Volker , ALBERTY, Thomas
发明人： ANT NACHRICHTENTECHNIK GMBH
IPC分类号： H04L07/02
CPC分类号： H04L7/0054 , H04L7/027
摘要： Process for timing synchronization in a digital data transmission receiver with a timing-error detector, to which are sent the in-phase component and quadrature component of the demodulated receiving signal from which the doubled frequency signal terms have been removed by low-pass filtering, and which acts as an input signal produced from the combination of the received signal with the output signal of the carrier oscillator. The output signal acts as a control signal uTI for the timing generator, the demodulated received signal being converted into two complex signals in the timing-error detector by means of two band-passes; said signals are coupled by a coupling circuit to form a control signal, which actuates the timing-error correction circuit; the process is characterized by the fact that the band-pass output signals are so coupled to form a second control signal uTR by means of a second coupling circuit that the two control signals uTR and uTI may be interpreted as the real part and the imaginary part of a complex actuation variable uT = uTR + juTI; also that the average A of the control signals uTR and uTI is calculated, and that finally the average value uTR, uTI thus achieved is calculated by a calculating circuit CC to achieve an actuating variable delta which controls the timing-error correction circuit TEC.
摘要翻译：具有定时误差检测器的数字数据传输接收机中的定时同步过程，向其发送经解调的接收信号的同相分量和正交分量，双通道频率信号项由此从低通滤波中去除，并且其用作从接收信号与载波振荡器的输出信号的组合产生的输入信号。输出信号用作定时发生器的控制信号uTI，经解调的接收信号通过两个带通转换成定时误差检测器中的两个复信号; 所述信号由耦合电路耦合以形成控制信号，其驱动定时误差校正电路; 该过程的特征在于，带通输出信号被耦合以通过第二耦合电路形成第二控制信号uTR，使得两个控制信号uTR和uTI可以被解释为实部和虚部的复合致动变量uT = uTR + juTI; 还计算出控制信号uTR和uTI的平均值A，并且最终通过计算电路CC计算由此获得的平均值uTR，uTI，以实现控制定时误差校正电路TEC的致动变量Δ。

3. 发明申请

WO1985002961A1 AUTOMATIC CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：自动时钟恢复电路
公开(公告)号：WO1985002961A1
公开(公告)日：1985-07-04
申请号：PCT/US1984001950
申请日：1984-11-29
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , BUTCHER, James, Steven
IPC分类号： H04L07/02
CPC分类号： H04L7/0331
摘要： An automatic clock recovery circuit (18). The automatic clock recovery circuit samples a received data signal with a recovered clock signal and advances or retards the recovered clock signal based on the comparison between the received data signal and the recovered clock signal. The automatic clock recovery ciruit (18) selectively cancels advance "A" or retard "R" corrections in the presence of bias distortion and phase ambiguities to improve the lock acquisition time for recovered clock.

4. 发明公开

EP0246530A3 Decoding system of data signals 失效
标题翻译：数据信号解码系统
公开(公告)号：EP0246530A3
公开(公告)日：1988-10-05
申请号：EP87106818
申请日：1987-05-11
申请人： Blaupunkt-Werke GmbH
发明人： Liman, Helmut
IPC分类号： H03L07/08 , G08G01/09 , H04L07/02
CPC分类号： G08G1/092 , H03L7/08 , H04L7/0083 , H04L7/033

5. 发明公开

EP0174125A3 Digital data receiver 失效
标题翻译：数字数据接收器
公开(公告)号：EP0174125A3
公开(公告)日：1988-06-15
申请号：EP85305841
申请日：1985-08-16
申请人： University of Toronto Innovations Foundation
发明人： Yen, Jui Lin , Wang, Rui
IPC分类号： H04L07/02 , H04L25/36
CPC分类号： H04L7/0029 , H04L7/005 , H04L25/05
摘要： @ A data receiving system for digital data communication is described which uses asynchronous sampling and language interpolation or prolate spheroidal function on the received signal. A received analogue signal is first asynchronously sampled (22), digitised (26), stored in memory (28) and then processed using interpolation techniques to recover the correct symbol timing of the symbols in the digitised data. The minimum sampling rate commensurate with channel band width is used. The correct symbol timing is continuously adjusted within certain predetermined limits of the interpolation interval using a "jumping" algorithm which permits continuous symbol recovery. The recovered symbols are then equalised (40) to compensate for distortion and decoded (44) to give the originally encoded data. When bursts of data are being transmitted the data stored in memory (28) is replayed to ensure that all data in the data burst is used for communication and that there is no transmission overhead requiring extra symbols for synchronisation. In one embodiment the received signal is used to generate real and imaginary components (32,34) which are then subjected to interpolation (36,38) and, the interpolation is controlled using a digital filter and algorithm which optimises filter coefficients to recover the symbol timing.

6. 发明公开

EP0179988A3 Circuit arrangement in telecommunication installations for synchronizing a locally generated clock signal with a clock signal received by way of digital information transmission telecommunication systems 失效
标题翻译：电话安排电路安装，用于同步通过数字信息传输方式接收的具有时钟信号的本地生成时钟信号电信系统
公开(公告)号：EP0179988A3
公开(公告)日：1987-06-24
申请号：EP85109665
申请日：1985-08-01
申请人： Telefonbau und Normalzeit GmbH
发明人： Artun, Berkan, Dipl.-Ing. , Goy, Helmut, Dipl.-Ing.
IPC分类号： H04L07/02 , H03L07/00
CPC分类号： H04L7/033

7. 发明公开

EP0173569A3 Receiver unit having synchronous pull-in circuit 失效
标题翻译：具有同步电源的接收器单元
公开(公告)号：EP0173569A3
公开(公告)日：1987-05-20
申请号：EP85306127
申请日：1985-08-29
申请人： FUJITSU LIMITED
发明人： Kaku, Takashi , Endo, Chihiro
IPC分类号： H04L07/02
CPC分类号： H04L7/007 , H04L7/0029 , H04L7/027
摘要： In a receiver unit such as a MODEM, a synchronous pull-in circuit is formed. The synchronous pull-in circuit comprises a transversal filter (4) having a roll-off characteristic, a timing discriminator (6) for extracting a timing signal contained in a received signal and a decision part (7) for detecting a phase deviation between the thus extracted timing signal and an internal clock by which the receiver unit is synchronized. The roll-off filter (4) is provided with a plurality of taps, the tap coefficients of which are varied by the decision part (7) via line (L,) in accordance with the phase deviation derived by the decision part (7), so that the timing signal is synchronized with the internal clock.

8. 发明公开

EP0080332A3 Full duplex modems and synchronizing methods and apparatus therefor 失效
标题翻译：全双工模式和同步方法及其设备
公开(公告)号：EP0080332A3
公开(公告)日：1983-09-14
申请号：EP82306151
申请日：1982-11-18
申请人： NOVATION INC
发明人： Ragsdale, Robert G.
IPC分类号： H04L07/02 , H04L27/06
CPC分类号： H04L7/0083 , H04L7/0062 , H04L27/38
摘要： Full duplex modems and synchronizing methods and apparatus therefor which allow the relatively low cost realization of full duplex modems compatible with prior art data sets such as the Bell System 212A Data Set. The modems utilize relatively little bandpass line filtering with post demodulation filters which provide normal filtering of second harmonic products, but further also serving to make up for the lack of the ordinarily heavy line or predemodulation filtering commonly used to reject the other channel. In addition, the automatic gain control is provided after the post demodulation filters rather than on the incoming line itself. Carrier sync and timing error corrections are provided under software control, with timing error corrections being achieved by sensing certain phase differences and providing a correction in response thereto. The use of switched capacitor filters, as well as other techniques herein disclosed, allows the use of two identical large scale integrated circuits to provide most of the transmit and receive functions of the modem.

9. 发明公开

EP0037260A3 Data regenerative system for NRZ mode signals 失效
标题翻译： NRZ模式信号的数据再生系统
公开(公告)号：EP0037260A3
公开(公告)日：1982-04-21
申请号：EP81301313
申请日：1981-03-26
申请人： VICTOR COMPANY OF JAPAN, LIMITED
发明人： Ito, Yasuo
IPC分类号： H04L25/52 , G11B05/09 , H04L07/02
CPC分类号： G11B20/10009 , H04L7/033 , H04L25/242
摘要： A data regenerative system adapted to receive data signals transmitted with the Non-Return-to-Zero mode comprises a comparator (10) for comparing the voltage level of the received data with a variable threshold to generate a digital comparator output. D-type flip-flops (DFF1, DFF2) are arranged to receive the comparator output to generate first and second pulses respectively in response to a data strobe clock pulse. The time difference between the first and second pulses is detected by a first subtractor (21, 22, 23) to generate an error voltage which is applied to the comparator (10) as its threshold to keep the crossing points of the eye pattern of the received signal aligned on the threshold level. A variable width monostable multivibrator (MM) is responsive to synchronization pulses to generate the data strobe clock pulses with a duration that is a function of an output of a second subtractor (26, 27, 28) representing the difference between each period of the first and second pulses and one-half period of a third pulse generated by a D-type flip-flop (DFF4) in response to the leading edge transition of the output of the monostable multivibrator (MM) in the presence of the first and second pulses. Output pulses are regenerated in response to the output of the monostable multivibrator in the presence of the comparator output.

10. 发明公开

EP0204308A3 Modem communication system having training means and method for training same 失效
标题翻译：具有培训手段的调制解调器通信系统及其培训方法
公开(公告)号：EP0204308A3
公开(公告)日：1988-11-30
申请号：EP86107506
申请日：1986-06-03
申请人： FUJITSU LIMITED
发明人： Kaku, Takashi , Arai, Yasuhiro
IPC分类号： H04L27/06 , H04L25/03 , H04L07/02
CPC分类号： H04L27/38 , H04L7/027 , H04L7/046 , H04L25/03133 , H04L2025/03783
摘要： A multipoint type MODEM communication system having a training device for adapting receiving parameters in a receiving MODEM (101) to a characteristic of a telephone line (300) connected to a sending MODEM in response to a training signal sent from the sending MODEM (201, 211, 222) prior to the reception of data. The training signal includes at least two impulses, a time between them defining the characteristic of the telephone line which should be adjusted in the receiving MODEM. The training signal may be superimposed on a tone and a timing signal, which are used for gain control and pull-in synchronization, and the impulses used for equalization and carrier-phase-control. The training signal also may include the tone, the timing signal, and the impulses in series. Additional guard impulses may be added prior to and/or after the impulses. A scramble signal also may be added after the impulses. In addition, a method for training the receiving MODEM is disclosed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式