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1. 发明授权

US06337648B1 MOS transistor digital-to-analog converter 有权
标题翻译： MOS晶体管数模转换器
公开(公告)号：US06337648B1
公开(公告)日：2002-01-08
申请号：US09440015
申请日：1999-11-12
申请人： Sami Kiriaki
发明人： Sami Kiriaki
IPC分类号： H03M178
CPC分类号： H03M1/785
摘要： A monolithic, low power, digital-to-analog converter (DAC) circuit which uses an efficient transistor element to perform both switching and resistive current division functions simultaneously. This allows a R-2R type ladder network to be built using only conventional MOS transistors which can both switch and accurately divide current among the branches of the ladder network, without the need for separate resistors. The lower parts count and requirement for MOS transistors only, without the need for separate resistors, makes this circuit very compatible with low cost monolithic implementation. The DAC of this patent is useful in an application requiring the multiplication of two analog signals, where one of the signals is presented as a digital word. In this application, a Gilbert multiplier circuit is used to multiply the two signals, Vdig and Vsig, where Vdig represents the binary-weighted discrete levels from the DAC and Vsig is a continuous analog signal. Additionally, in order to obtain linear multiplication over a wide range, the Gilbert multiplier requires the use of a predistortion circuit in conjunction with the Vdig signal coming from the DAC to compensate for the logarithmic current-voltage transfer function of this circuit.
摘要翻译：一种单片，低功耗，数模转换器（DAC）电路，其使用有效的晶体管元件同时执行开关和电阻分流功能。这使得仅使用常规的MOS晶体管来构建R-2R型梯形网络，其可以在梯形网络的分支之间切换和精确地分配电流，而不需要单独的电阻器。仅对MOS晶体管的低部件数量和要求，而不需要单独的电阻器，使得该电路与低成本的单片实现非常兼容。该专利的DAC在需要两个模拟信号的乘法的应用中是有用的，其中一个信号被呈现为数字字。在本应用中，吉尔伯特乘法器电路用于乘以Vdig和Vsig两个信号，其中Vdig表示来自DAC的二进制加权离散电平，Vsig是连续的模拟信号。另外，为了在宽范围内获得线性乘法，吉尔伯特乘法器需要结合来自DAC的Vdig信号使用预失真电路来补偿该电路的对数电流 - 电压传递函数。

2. 发明授权

US06567026B1 Voltage scaling digital-to- analog converter with impedance strings 有权
标题翻译：具有阻抗线的电压调节数模转换器
公开(公告)号：US06567026B1
公开(公告)日：2003-05-20
申请号：US09990584
申请日：2001-11-21
申请人： Christopher Matthew Gorman
发明人： Christopher Matthew Gorman
IPC分类号： H03M178
CPC分类号： H03M1/682 , H03M1/765
摘要： A DAC (1) comprises a pair of outer strings (4,5) of resistors Ra and Rb and an inner string (12) of resistors Rc connected in series with the outer string (4,5). The inner string (12) converts the LSBs, while the outer strings convert the MSBs. Outer switch networks (10,11) of switches Sa and Sb selectively switch the outer strings (4,5) to reference voltage terminals Vref+ and Vref− (8,9) for selectively coupling selected portions of the outer strings (4,5) to the respective voltage reference terminals (8,9) for decrementing the inner string (12) in steps corresponding to one MSB between the terminals (8,9). An inner switch network (15) of switches Sc selectively connects an analog output terminal (2) to one of the resistors Rc; corresponding to the LSBs so that the analog voltage on the output terminal corresponds to the digital input signal.
摘要翻译： DAC（1）包括电阻器Ra和Rb的一对外部串（4,5）和与外部串（4,5）串联连接的电阻器Rc的内部串（12）。内部字符串（12）转换LSB，而外部字符串转换MSB。开关Sa和Sb的外部开关网络（10,11）有选择地将外部串（4,5）切换到参考电压端子Vref +和Vref-（8,9），用于选择性地耦合外部串（4,5）的选定部分，到各个电压基准端子（8,9），用于在对应于端子（8,9）之间的一个MSB的步骤中递减内部串（12）。开关Sc的内部开关网络（15）选择性地将模拟输出端子（2）连接到电阻器Rc之一; 对应于LSB，使得输出端子上的模拟电压对应于数字输入信号。

3. 发明授权

US06380878B1 Digital-to-analog conversion circuit 有权
标题翻译：数模转换电路
公开(公告)号：US06380878B1
公开(公告)日：2002-04-30
申请号：US09920445
申请日：2001-08-01
申请人： Carlo Pinna
发明人： Carlo Pinna
IPC分类号： H03M178
CPC分类号： H03M1/0665 , H03M1/747 , H03M3/502
摘要： The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal. In an embodiment the digital to analog conversion circuit able to transform a digital input signal having n bit in an output analog signal comprise: a thermometric decoder having said digital input signal in input and able to produce said signal having a thermometric code with 2n−1 bit in output; a digital to analog converter with modular elements including 2n−1 controlled switches; a shift register able to receive said digital signal having 2n−1 bit in an data input and able to produce 2n−1 control signals of said controlled switches in output; a delay circuit of said of digital input signal having the output connected to a shift input of said shift register and able to produce a delayed digital signal in output as to make said digital signal having 2n−1 bit shift by a number of bit equal to the value of said delayed digital signal; characterized by further comprising a generator of a digital random number selected in a range of prefixed values and having a prefixed probability of occurrence; an adder node able to receive said random digital number and said delayed digital signal in input whose output is connected to said shift input of said shift register.
摘要翻译：本发明涉及一种数模转换电路，能够对具有测温码的信号中具有n位的输入数字信号进行变换，并将其转换为模拟输出信号。在一个实施例中，能够对输出模拟信号中具有n位的数字输入信号进行变换的数模转换电路包括：温度测量解码器，其具有输入中的所述数字输入信号，能够产生具有2n-1的测温码的所述信号位输出; 具有模块化元件的数模转换器，包括2n-1个受控开关; 移位寄存器，其能够接收在数据输入中具有2n-1位的所述数字信号，并且能够在输出中产生所述受控开关的2n-1个控制信号; 所述数字输入信号的延迟电路具有连接到所述移位寄存器的移位输入的输出，并且能够在输出中产生延迟的数字信号，以使所述数字信号具有2n-1位移位等于所述延迟数字信号的值; 其特征在于还包括在预定值的范围内选择并且具有预先出现的概率的数字随机数的发生器; 加法器节点能够接收所述随机数字数字和输入中的所述延迟数字信号，其输出端连接到所述移位寄存器的所述移位输入。

4. 发明授权

US06268819B1 Bit interpolation in a resistor string data converter 有权
标题翻译：电阻串数据转换器中的位插值
公开(公告)号：US06268819B1
公开(公告)日：2001-07-31
申请号：US09342878
申请日：1999-06-29
申请人： John W. Fattaruso , Shivaling S Mahant-Shetti
发明人： John W. Fattaruso , Shivaling S Mahant-Shetti
IPC分类号： H03M178
CPC分类号： H03M1/765
摘要： A data converter (20). The converter comprises an input (I0-I3) for receiving a digital word. The converter further comprises a string (22) of series connected resistive elements. The string comprises an integer number T of voltage taps (T0′-T8′). The converter further comprises an output (VOUT2) for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T.
摘要翻译：数据转换器（20）。转换器包括用于接收数字字的输入（I0-I3）。转换器还包括串联电阻元件串（22）。该串包括整数T的电压抽头（T0'-T8'）。转换器还包括用于响应于数字字提供不同模拟电压电平的整数P的输出（VOUT2）。整数P大于整数T.

5. 发明授权

US06222473B1 Method and apparatus for digital to analog converters with improved switched R-2R ladders 有权
标题翻译：具有改进的开关R-2R梯形的数模转换器的方法和装置
公开(公告)号：US06222473B1
公开(公告)日：2001-04-24
申请号：US09299691
申请日：1999-04-26
申请人： David Castaneda , Gary G. Fang , Chowdhury F. Rahim
发明人： David Castaneda , Gary G. Fang , Chowdhury F. Rahim
IPC分类号： H03M178
CPC分类号： H03M1/06 , H03M1/785
摘要： Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.
摘要翻译：通过增加与终端脚中的终端开关串联的电阻来改善数模转换器（DAC）的R-2R级梯形图的工作范围，以避免晶体管饱和，从而提高DAC分辨率，增加参考电压范围或其他应用。修改了开关式R-2R梯形电路，以补偿增加的电阻，以保持适当的电阻匹配，以产生数字输入信号的适当范围的模拟输出电压。

6. 发明授权

US06710731B1 Apparatus and method for a digital to analog converter architecture 有权
标题翻译：用于数模转换器架构的装置和方法
公开(公告)号：US06710731B1
公开(公告)日：2004-03-23
申请号：US09954543
申请日：2001-09-10
申请人： Anurag Kaplish , John A. Tabler
发明人： Anurag Kaplish , John A. Tabler
IPC分类号： H03M178
CPC分类号： H03M1/0607 , H03M1/68 , H03M1/76
摘要： Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.
摘要翻译：数模转换器架构保证了整体非线性的单调性和部分补偿。两个级由单位增益运算放大器分开，其中第一级是1位电阻串转换器，在参考高电压下具有一端，另一端为基准低电压，第二级为多位位电阻串转换器。该架构减轻了1位前端所需的匹配精度。电阻失配通过变化的缓冲放大器偏置电压来补偿，并确保放大器输出在参考电压之间的一半; 这通过电阻串中存在的失配量来提高积分非线性或绝对精度。 DAC的第二级输出缓冲放大器通过改变失调电压来控制INL误差。

7. 发明授权

US06642873B1 Multi-level D/A converter incorporated with multi-level quantizer in multi-bit sigma-delta A/D converter 失效
标题翻译：在多位Σ-ΔA / D转换器中并入多电平量化器的多电平D / A转换器
公开(公告)号：US06642873B1
公开(公告)日：2003-11-04
申请号：US10159671
申请日：2002-06-03
申请人： Wensheng Vincent Kuang
发明人： Wensheng Vincent Kuang
IPC分类号： H03M178
CPC分类号： H03M3/424 , H03M1/365 , H03M1/765 , H03M3/464
摘要： A Multi-level digital-to-analog (D/A) converter is incorporated with a multi-level quantizer in a multi-bit sigma-delta analog-to-digital (A/D) converter. The multi-level D/A converter is realized by feeding back reference voltages of the multi-level quantizer through a switch. The summation of electrical energy from multiple D/A converter elements found in conventional D/A converters is avoided so that element mismatch and circuit complexity are reduced significantly in the multi-bit sigma-delta A/D converter.
摘要翻译：多级数模（D / A）转换器与多位Σ-Δ模数（A / D）转换器中的多电平量化器并入。多电平D / A转换器通过交换机反馈多电平量化器的参考电压来实现。避免了在常规D / A转换器中发现的来自多个D / A转换器元件的电能的总和，使得在多位Σ-ΔA/ D转换器中元件失配和电路复杂度显着降低。

8. 发明授权

US06639536B2 Digital-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US06639536B2
公开(公告)日：2003-10-28
申请号：US10361625
申请日：2003-02-11
申请人： Atsushi Matsuda , Tohru Mizutani
发明人： Atsushi Matsuda , Tohru Mizutani
IPC分类号： H03M178
CPC分类号： H03M1/662 , H03M1/765
摘要： First and second switches are connected at each node between adjacent resistors in a resistor row and at the end of the resistor row. A predetermined number of first switches are grouped together and short-circuited to obtain a plurality of first switch groups, and a predetermined number of second switches are grouped together and short-circuited to obtain a plurality of second switch groups. The first and second switch groups are connected to output terminals via output switches. The first and second switches are ON/OFF controlled such that only one switch in the first and second switch groups is connected to the resistance row.
摘要翻译：第一和第二开关连接在电阻器行中和电阻器行末端的相邻电阻器之间的每个节点处。将预定数量的第一开关分组在一起并短路以获得多个第一开关组，并且将预定数量的第二开关分组在一起并进行短路以获得多个第二开关组。第一和第二开关组通过输出开关连接到输出端。第一和第二开关被控制为使得第一和第二开关组中只有一个开关连接到电阻排。

9. 发明授权

US06384763B1 Segemented D/A converter with enhanced dynamic range 有权
标题翻译：具有增强动态范围的分段D / A转换器
公开(公告)号：US06384763B1
公开(公告)日：2002-05-07
申请号：US09583341
申请日：2000-05-31
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H03M178
CPC分类号： H03M1/0602 , H03M1/682 , H03M1/765
摘要： A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.
摘要翻译：具有串联连接的晶体管的数模转换器形成用于各个分段电阻串的高阻抗电流源。形成用于一个电阻器串的电流吸收器的串联晶体管通过利用负反馈放大器呈现高输出阻抗。通过使用适当的增益电阻配置输出放大器，可以消除一个电阻串中的裕量电阻和偏移电阻的影响。通过使用相同值的主电阻和子电阻串的所有电阻，可以实现高精度的D / A转换。

10. 发明授权

US06380876B1 D/A conversion circuit and semiconductor device 有权
标题翻译： D / A转换电路和半导体器件
公开(公告)号：US06380876B1
公开(公告)日：2002-04-30
申请号：US09571612
申请日：2000-05-15
申请人： Shou Nagao
发明人： Shou Nagao
IPC分类号： H03M178
CPC分类号： H03M1/0682 , H03M1/068 , H03M1/808
摘要： A DAC whose area is held down and a semiconductor device using the DAC are fabricated. A D/A conversion circuit is disclosed, including n resistors A0, A1, . . . An−1, n resistors B0, B1, . . . , Bn−1, two power-supply voltage lines, a power-supply voltage line L and a power-supply voltage line H, maintained at potentials different from each other, n switches SWa0, SWa1, . . . , SWan−1, n switches SWb0, SWb1, . . . , SWbn−1, and an output line, wherein, by n-bit digital signals inputted from the outside, said n switches SWa0, SWa1, . . . , SWan−1 and said n switches SWb0, SWb1, . . . , SWbn−1 are controlled, and, from the output line, an analog gradation voltage signal is outputted.
摘要翻译：制造其面积被压缩的DAC和使用DAC的半导体器件。公开了一种D / A转换电路，包括n个电阻器A0，A1。。。 An-1，n电阻器B0，B1，。。。，Bn-1，两个电源电压线，电源电压线L和电源电压线H保持彼此不同的电位，n切换SWa0，SWa1。。。，SWan-1，n开关SWb0，SWb1，。。。，SWbn-1和输出线，其中，通过从外部输入的n位数字信号，所述n个开关SWa0，SWa1，...。。。，SWan-1和所述n个开关SWb0，SWb1，...。。。，SWbn-1被控制，并且从输出线输出模拟灰度电压信号。

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