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1. 发明授权

US06445319B1 Analog to digital converter circuit 有权
标题翻译：模数转换电路
公开(公告)号：US06445319B1
公开(公告)日：2002-09-03
申请号：US09569118
申请日：2000-05-10
申请人： Alexander R. Bugeja
发明人： Alexander R. Bugeja
IPC分类号： H03M162
CPC分类号： H03M1/1038 , H03M1/1004 , H03M1/12
摘要： An analog-to-digital converter (ADC) (12) having a nonlinear transfer function with a unique mapping. The ADC (12) is adapted to produce a digital output signal for a plurality of analog input signals, and a transfer function modifying circuit (14) is coupled to the ADC circuit (13). The transfer function modifying circuit (14) is adapted to modify the ADC circuit (13) transfer function (34) to have a unique mapping. The ADC (12) transfer function has multiple transfer function segments with varying slopes. Further disclosed is a method for designing an ADC (12) having a nonlinear transfer function, and a method for calibrating an ADC (12).
摘要翻译：具有具有独特映射的非线性传递函数的模数转换器（ADC）（12）。 ADC（12）适于产生用于多个模拟输入信号的数字输出信号，并且传递函数修正电路（14）耦合到ADC电路（13）。传递函数修改电路（14）适于修改ADC电路（13）传递函数（34）以具有唯一的映射。 ADC（12）传递函数具有多个具有不同斜率的传递函数段。还公开了一种用于设计具有非线性传递函数的ADC（12）的方法和用于校准ADC（12）的方法。

2. 发明授权

US06670901B2 Dynamic range on demand receiver and method of varying same 有权
标题翻译：动态范围点播接收机和不同方法
公开(公告)号：US06670901B2
公开(公告)日：2003-12-30
申请号：US09919554
申请日：2001-07-31
申请人： Daniel E. Brueske , Babak Bastani
发明人： Daniel E. Brueske , Babak Bastani
IPC分类号： H03M162
CPC分类号： H04B1/0032 , H03G3/3052 , H04B1/0003 , H04B1/0039 , H04B1/109
摘要： A dynamic range on demand radio frequency (RF) receiver (300) includes a wideband detector (303), off-channel detector (313) and on-channel detector (327) supplying input to an automatic gain control (307) for adjusting a dynamic control stage to control dynamic range and resolution of digital baseband signals (329, 331).
摘要翻译：动态范围点播射频（RF）接收机（300）包括向自动增益控制器（307）提供输入的宽带检测器（303），离线通道检测器（313）和通道检测器（327）动态控制级控制数字基带信号的动态范围和分辨率（329,331）。

3. 发明授权

US06411235B1 Dynamic range extension with gain correction 有权
标题翻译：动态范围扩展与增益校正
公开(公告)号：US06411235B1
公开(公告)日：2002-06-25
申请号：US09602747
申请日：2000-06-23
申请人： Aravanan Gurusami , Joseph F. Chiappetta , Niranjan Samant , Donald T. Wesson
发明人： Aravanan Gurusami , Joseph F. Chiappetta , Niranjan Samant , Donald T. Wesson
IPC分类号： H03M162
CPC分类号： H04W52/52 , H03G3/3036
摘要： A method for controlling gain in a network is provided. The method includes receiving signals for transmission over a network and adjusting the level of the received signals. The method further includes inserting an additional signal indicative of the level adjustment and transmitting the signals and the additional signal over the network. The method also includes extracting the additional signal after transmission over the network and compensating for the level adjustment based on the extracted signal.
摘要翻译：提供了一种用于控制网络中的增益的方法。该方法包括接收通过网络传输的信号并调整接收信号的电平。该方法还包括插入指示电平调整的附加信号，并通过网络发送信号和附加信号。该方法还包括在通过网络传输之后提取附加信号，并且基于提取的信号补偿电平调整。

4. 发明授权

US06295013B1 Nonlinear flash analog to digital converter used in an active pixel system 有权
标题翻译：在有源像素系统中使用的非线性闪光模数转换器
公开(公告)号：US06295013B1
公开(公告)日：2001-09-25
申请号：US09161355
申请日：1998-09-25
申请人： Sandor Barna , Daniel Van Blerkam , Eric R. Fossum
发明人： Sandor Barna , Daniel Van Blerkam , Eric R. Fossum
IPC分类号： H03M162
CPC分类号： H03M1/367 , H04N5/378
摘要： A non-uniform resistor is used with a flash A to D converter in order to provide an A to D output which is not linear. The nonlinearity of the A to D output is specially designed to carry out a predetermined correction of the signal.
摘要翻译：闪光A到D转换器使用不均匀的电阻，以提供不是线性的A到D输出。 A到D输出的非线性特别设计用于执行信号的预定校正。

5. 发明授权

US06259391B1 Analog gain control adjustment using a probabilistic algorithm 有权
标题翻译：使用概率算法进行模拟增益控制调整
公开(公告)号：US06259391B1
公开(公告)日：2001-07-10
申请号：US09335836
申请日：1999-06-18
申请人： Mohammed Reza Pakravan , Gwendolyn Kate Harris
发明人： Mohammed Reza Pakravan , Gwendolyn Kate Harris
IPC分类号： H03M162
CPC分类号： H03M1/185
摘要： A method and apparatus for adjusting the amplitude of a received discrete multi-tone analog signal contaminated by radio frequency interference from radio stations in the AM band are described. The amplitude is adjusted by controlling an analog gain controller in order to utilize substantially all of a dynamic input range of an analog-to-digital converter to reduce the quantization noise of the output digital signal. Data discrimination is truly improved and the capacity of usable discrete multi-tone channels is increased.
摘要翻译：描述了用于调整受AM频带中的无线电台的射频干扰所污染的接收离散多音调模拟信号的振幅的方法和装置。通过控制模拟增益控制器来调整振幅，以便利用模数转换器的基本上所有的动态输入范围来减小输出数字信号的量化噪声。真正提高数据鉴别，提高可用离散多音频通道的容量。

6. 发明授权

US06191716B1 High-speed digital circuit employing a band-zero-determination-aside (BØDA) architecture 有权
标题翻译：采用频带零测定（BØDA）架构的高速数字电路
公开(公告)号：US06191716B1
公开(公告)日：2001-02-20
申请号：US09322671
申请日：1999-05-28
申请人： Robert B. Staszewski
发明人： Robert B. Staszewski
IPC分类号： H03M162
CPC分类号： G11B20/10 , G11B20/10009
摘要： A system and a method for calculating a value for the “Band Zero” (B∅) contribution to the processing of a digital signal by processing the separate parts of the signal at separate times. The method increases operating speed of a feedback circuit, for example, by providing a processing path (402f) that is not on the main high-speed processing path of a system such as a read channel of a disk drive. By processing the most time-consuming determination “in parallel,” the high-speed portion of processing is able to maintain an optimum throughput. The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel (113) of a disk drive (100) employing a FIR filter, three modes are desired: FIR-bypass, acquisition, and data tracking. Being able to switch easily among the three modes provided for in a read channel (113) of a disk drive (100) demonstrates the adaptability of the method and supporting structure to a broad class of feedback circuits used in systems employing high throughput rates.
摘要翻译：一种系统和方法，用于通过在分开的时间处理信号的单独部分来计算“频带零”（B∅）对数字信号的处理贡献的值。该方法例如通过提供不在诸如盘驱动器的读通道的系统的主高速处理路径上的处理路径（402f）来提高反馈电路的操作速度。通过并行处理最耗时的决定，高速部分处理能够保持最佳的吞吐量。该方法还适用于那些使用多种模式的应用程序中的处理。例如，当在采用FIR滤波器的盘驱动器（100）的读通道（113）中使用时，需要三种模式：FIR旁路，采集和数据跟踪。能够容易地在盘驱动器（100）的读通道（113）中提供的三种模式之间切换，这表明该方法和支持结构适用于采用高吞吐率的系统中广泛使用的反馈电路。

7. 发明授权

US06633247B2 Logarithmic a/d converter, method of logarithmic a/d conversion logarithmic d/a converter, method of logarithmic d/a conversion, and system for measuring physical quantity 失效
标题翻译：对数a / d转换器，对数a / d转换对数d / a转换器的方法，对数d / a转换方法和物理量测量系统
公开(公告)号：US06633247B2
公开(公告)日：2003-10-14
申请号：US09958567
申请日：2001-11-27
申请人： Masami Yakabe
发明人： Masami Yakabe
IPC分类号： H03M162
CPC分类号： H03M1/664 , H03M1/367
摘要： An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.
摘要翻译：模拟乘法器 11 将基准参考电压“Vref 0 ”提升到第n个功率，使得参考电压“Vref 1 “。模拟乘法器 12 和 13 依次提升参考电压“Vref 1 PDAT>“到第n个功率，从而产生参考电压”Vref 2 “和”Vref 3 “。开关组 38-41 将参考电压“Vref 0 ”控制为“Vref 3 < / BOLD> “，然后将它们与输入电压”Vin“一起发送到模拟乘法器 14 。比较器 14 将乘法器 14 的乘法结果“Vx”与从传感器电路 2，，从而产生数字输出值“Dout”。模拟乘法器 14 根据需要设置。

8. 发明授权

US06545620B2 Current-to-voltage converter with controllable gain, and signal processing circuit comprising such a converter 有权
标题翻译：具有可控增益的电流 - 电压转换器和包括这种转换器的信号处理电路
公开(公告)号：US06545620B2
公开(公告)日：2003-04-08
申请号：US09781487
申请日：2001-02-12
申请人： Willem Hendrik Groeneweg
发明人： Willem Hendrik Groeneweg
IPC分类号： H03M162
CPC分类号： H03M3/504
摘要： Summarizing, the present invention provides an IVC (100), comprising an operational amplifier (110) with an inverting input (112) and an output (113), and a feedback resistor ladder network (120) coupled between the output (113) and the inverting input (112). The feedback resistor ladder network (120) comprises a main chain (121) composed of a plurality of substantially identical unit resistors (RU) connected in series, and a plurality of branches (124i), each branch (124i) coupling a node (Xi) in the main chain (121) to the inverting input (112) of the operational amplifier (110), each branch (124i) comprising a selectable feedback switch (123i). Further, some of the branches (124i) comprise a non-unit resistor (RNUi) coupled in series with the corresponding selectable feedback switch (123i). Further, the present invention provides a circuit comprising a FIRDAC (20) and a bias block (30) for providing at least one bias current for the FIRDAC (20). The bias block (30) comprises at least one bias resistor (RB). The FIRDAC (20) is associated with at least one IVC (25, 26), configured as described above, wherein the unit resistors (RU) of the at least one IVC (25, 26) are substantially identical to the bias resistor (RB) of the bias block (30).
摘要翻译：总之，本发明提供了一种IVC（100），其包括具有反相输入（112）和输出（113）的运算放大器（110）和耦合在输出（113）和反相输入端（112）。反馈电阻梯形网络（120）包括由串联连接的多个基本相同的单位电阻器（RU）组成的主链（121）和多个分支（124i），每个分支（124i）耦合节点（Xi ）到运动放大器（110）的反相输入端（112）的主链（121）中，每个分支（124i）包括可选择的反馈开关（123i）。此外，一些分支（124i）包括与相应的可选择反馈开关（123i）串联耦合的非单位电阻器（RNUi）。此外，本发明提供一种包括FIRDAC（20）和偏置块（ 30），用于为FIRDAC（20）提供至少一个偏置电流。偏置块（30）包括至少一个偏置电阻器（RB）。 FIRDAC（20）与至少一个如上所述配置的IVC（25,26）相关联，其中至少一个IVC（25,26）的单位电阻器（RU）与偏置电阻器（RB）基本相同）偏置块（30）。

9. 发明授权

US06445320B1 A/D conversion apparatus 有权
标题翻译： A / D转换装置
公开(公告)号：US06445320B1
公开(公告)日：2002-09-03
申请号：US09492442
申请日：2000-01-27
申请人： Masao Noro , Akira Sogo , Ryo Kamiya
发明人： Masao Noro , Akira Sogo , Ryo Kamiya
IPC分类号： H03M162
CPC分类号： H03M3/49
摘要： An A/D conversion apparatus is provided, which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels. An input gain control device controls gain of an input signal based on a control signal. A &Dgr;&Sgr; modulator carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit. A detecting device detects a peak value of the input signal based on the data of one bit. A gain control device generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range. To effectively reduce noise of the output digital signal while securing a wide dynamic range of A/D conversion, the &Dgr;&Sgr; modulator may also control the gain of the input signal based on the control signal to a predetermined value (1/A) smaller than 1, and the decimation circuit may have a gain of a second predetermined value (A) for compensating for the gain of the input signal controlled to the predetermined value (1/A).
摘要翻译：提供了一种A / D转换装置，其能够通过在预定电平之间适当地切换输入模拟信号的输入增益，以简单的结构确保宽动态范围的A / D转换。输入增益控制装置基于控制信号来控制输入信号的增益。 DELTASIGMA调制器对输入信号进行过采样，该输入信号的增益由输入增益控制装置控制，以将输入信号转换成一位的数据。检测装置根据一位的数据来检测输入信号的峰值。增益控制装置基于由检测装置检测的峰值以使得其控制增益的输入信号落在预定范围内的方式产生控制信号。为了有效地降低输出数字信号的噪声，同时确保宽的动态范围的A / D转换，DELTASIGMA调制器还可以基于控制信号将输入信号的增益控制到小于1的预定值（1 / A），并且抽取电路可以具有用于补偿被控制到预定值（1 / A）的输入信号的增益的第二预定值（A）的增益。

10. 发明授权

US06392574B1 System and method for exponential digital to analog conversion 有权
标题翻译：用于指数数模转换的系统和方法
公开(公告)号：US06392574B1
公开(公告)日：2002-05-21
申请号：US09306739
申请日：1999-05-07
申请人： Zabih Toosky
发明人： Zabih Toosky
IPC分类号： H03M162
CPC分类号： H03M1/664 , H03M1/745
摘要： The present invention relates to digital to analog conversion. According to an embodiment of the present invention, an exponential transfer characteristic may be produced by adding a fraction of the output current to a reference current in a recursive equation.
摘要翻译：本发明涉及数模转换。根据本发明的实施例，可以通过在递归方程中将一部分输出电流加到参考电流来产生指数传递特性。

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