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1. 发明授权

US06332209B1 Method for a general turbo code trellis termination 有权
标题翻译：一般turbo码格局终止的方法
公开(公告)号：US06332209B1
公开(公告)日：2001-12-18
申请号：US09378625
申请日：1999-08-20
申请人： Mustafa Eroz , A. Roger Hammons, Jr.
发明人： Mustafa Eroz , A. Roger Hammons, Jr.
IPC分类号： H03M1323
CPC分类号： H03M13/6362 , H03M13/2903 , H03M13/2993 , H03M13/2996 , H03M13/4123
摘要： A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.
摘要翻译：一种终止采用turbo码的turbo编码器的两个或更多个组成编码器的方法，包括以下步骤：在两个或更多个组成编码器中的每一个处产生尾部输入位，包括从两个或更多个成分中的每一个导出尾部输入位在两个或多个组成编码器对信息比特进行编码之后，与两个或更多个组成编码器中的每一个中的移位寄存器的内容分开编码; 对一个或多个尾部输出位进行穿孔，使得对于多个网格分支中的每一个发送1 / R个输出尾比特，其中R是在信息比特传输期间由turbo编码器采用的turbo码率。在另一个实施例中，打孔尾部输出位的步骤还包括以下步骤：在网格终止期间，仅在从两个或更多个组成编码器之一的输出分支发送尾部输出位时发送尾部输出位，在信息位传输期间使用。

2. 发明授权

US06697994B2 Operation processing apparatus and operation processing method 有权
标题翻译：操作处理装置和操作处理方法
公开(公告)号：US06697994B2
公开(公告)日：2004-02-24
申请号：US10305946
申请日：2002-11-29
申请人： Toshihiro Ishikawa
发明人： Toshihiro Ishikawa
IPC分类号： H03M1323
CPC分类号： H03M13/235 , H03M13/27 , H03M13/2903 , H03M13/2957
摘要： Shift register stores data read from data memory through data bus, and supplies a shift output to shift register. Shift register stores operation target data read from data memory through data bus, shifts operation target data one bit by one bit, and supplies operation target data to bit selection circuit. Bit selection circuit selects bit data, which is placed at a position designated by register, from data stored in shift register. Multi-input exclusive OR circuit executes exclusive OR operations of all bits of bit data output from bit selection circuit, simultaneously, and outputs an operation result of one bit to shift register. This makes it possible to efficiently perform convolutional code processing at high speed.
摘要翻译：移位寄存器通过数据总线存储从数据存储器读取的数据，并将移位输出提供给移位寄存器。移位寄存器存储从数据存储器通过数据总线读取的操作对象数据，一个位移位操作对象数据，并将操作对象数据提供给位选择电路。位选择电路从存储在移位寄存器中的数据中选择放置在由寄存器指定的位置的位数据。多输入异或电路同时执行从位选择电路输出的位数据的所有位的异或运算，并将一位的运算结果输出到移位寄存器。这使得可以高效地执行卷积码处理。

3. 发明授权

US06460159B1 Device and method for convolutional encoding in digital system 有权
标题翻译：数字系统卷积编码的装置及方法
公开(公告)号：US06460159B1
公开(公告)日：2002-10-01
申请号：US09476436
申请日：1999-12-30
申请人： Min-Goo Kim , Beong-Jo Kim , Young-Hwan Lee , Soon-Jae Choi
发明人： Min-Goo Kim , Beong-Jo Kim , Young-Hwan Lee , Soon-Jae Choi
IPC分类号： H03M1323
CPC分类号： H04L1/0069 , H03M13/03 , H04L1/0041
摘要： A convolutional encoding device and method in a digital system. According to an embodiment of the present invention, a convolutional encoding device has a convolutional encoder and a puncturer. The convolutional encoder generates a subgroup of a first, a second and a third encoded symbols for each input bit using generator polynomials including g0(x)=1+x2+x3+x5+x6+x7+x8, g1(x)=1+x +x3+x4+x7+x8, and g2(x)=1+x+x2+x5+x8, for inputting input bits to generate a symbol group of three subgroups for three successive input bits, and for generating a stream of the symbol groups. A symbol puncturer punctures the first symbol of one of three subgroups in each symbol group generated from the convolutional encoder.
摘要翻译：数字系统中的卷积编码装置和方法。根据本发明的实施例，卷积编码装置具有卷积编码器和穿刺器。卷积编码器使用生成多项式生成包括g0（x）= 1 + x2 + x3 + x5 + x6 + x7 + x8，g1（x）= 1）的每个输入位的第一，第二和第三编码符号的子组 + x + x3 + x4 + x7 + x8和g2（x）= 1 + x + x2 + x5 + x8，用于输入输入位以产生三个连续输入位的三个子组的符号组，的符号组。符号穿孔器对从卷积编码器生成的每个符号组中的三个子组之一的第一符号进行穿孔。

4. 发明授权

US06397367B1 Device and methods for channel coding and rate matching in a communication system 有权
标题翻译：通信系统中的信道编码和速率匹配的装置和方法
公开(公告)号：US06397367B1
公开(公告)日：2002-05-28
申请号：US09326891
申请日：1999-06-07
申请人： Chang-Soo Park , Hyeon-Woo Lee
发明人： Chang-Soo Park , Hyeon-Woo Lee
IPC分类号： H03M1323
CPC分类号： H03M13/2957 , H03M13/3994 , H03M13/6356 , H03M13/6362 , H04L1/0066 , H04L1/0069
摘要： A channel coding device is disclosed. In the device, a bit inserter inserts known bits in an input data bit stream at predetermined positions. A channel coder codes the bit-inserted data bit stream to generate coded symbols. A rate matcher matches a rate of the coded symbols to a given channel symbol rate. A channel interleaver interleaves the rate matched channel symbols. The rate matcher includes a puncturer for puncturing the inserted known bits included in the coded symbols when the coded symbol rate is higher than the given channel symbol rate. The rate matcher includes a repeater for repeating the coded symbols to match the coded symbol rate to the given channel symbol rate when the coded symbol rate is lower than the given channel symbol rate.
摘要翻译：公开了一种信道编码装置。在该装置中，位插入器将预定位置的输入数据位流中的已知位插入。信道编码器对位插入数据比特流进行编码以生成编码符号。速率匹配器将编码符号的速率与给定的信道符号速率相匹配。信道交织器交织速率匹配信道符号。速率匹配器包括穿孔器，用于当编码符号率高于给定信道符号率时，对包含在编码符号中的插入的已知位进行删截。速率匹配器包括一个中继器，用于在编码符号速率低于给定信道符号率时重复编码符号以将编码符号速率与给定信道符号速率相匹配。

5. 发明授权

US06199190B1 Convolution decoding terminated by an error detection block code with distributed parity bits 失效
标题翻译：卷积解码由具有分布式奇偶校验位的错误检测块代码终止
公开(公告)号：US06199190B1
公开(公告)日：2001-03-06
申请号：US09021896
申请日：1998-02-11
申请人： Yongbing Wan
发明人： Yongbing Wan
IPC分类号： H03M1323
CPC分类号： H03M13/29 , A61B5/6882 , H03M13/23 , H03M13/27
摘要： An improved encoding technique improves the error detection provided in conventional communication systems. Traditional encoding systems for communication systems often utilize channel-coding in the form of block-coding and convolutional encoding. Block-coding typically utilizes parity bits for error detection. These parity bits are typically placed as a block at the end of the data frame. The present invention provides an improved encoder and decoder which utilize parity bits placed within the data and spread within the data bits for higher reliability.
摘要翻译：改进的编码技术改进了传统通信系统中提供的错误检测。用于通信系统的传统编码系统通常以块编码和卷积编码的形式利用信道编码。块编码通常使用用于错误检测的奇偶校验位。这些奇偶校验位通常在数据帧结束时放置为一个块。本发明提供了一种改进的编码器和解码器，其利用位于数据内的奇偶校验位并在数据位中扩展以提高可靠性。

6. 发明授权

US06523146B1 Operation processing apparatus and operation processing method 有权
标题翻译：操作处理装置和操作处理方法
公开(公告)号：US06523146B1
公开(公告)日：2003-02-18
申请号：US09449831
申请日：1999-11-26
申请人： Toshihiro Ishikawa
发明人： Toshihiro Ishikawa
IPC分类号： H03M1323
CPC分类号： H03M13/235 , H03M13/27 , H03M13/2903 , H03M13/2957
摘要： Shift register 5 stores data read from data memory 1 through data bus 3, and supplies a shift output to shift register 4. Shift register 4 stores operation target data read from data memory 1 through data bus 3, shifts operation target data one bit by one bit, and supplies operation target data to bit selection circuit 7. Bit selection circuit 7 selects bit data, which is placed at a position designated by register 6, from data stored in shift register 4. Multi-input exclusive OR circuit 8 executes exclusive OR operations of all bits of bit data output from bit selection circuit 7, simultaneously, and outputs an operation result of one bit to shift register 9. This makes it possible to efficiently perform convolutional code processing at high speed.
摘要翻译：移位寄存器5存储从数据存储器1通过数据总线3读取的数据，并将移位输出提供给移位寄存器4.移位寄存器4存储从数据存储器1通过数据总线3读取的操作目标数据，一个一个地移位操作目标数据位，并将操作对象数据提供给位选择电路7.位选择电路7从存储在移位寄存器4中的数据中选择放置在由寄存器6指定的位置的位数据。多输入异或电路8执行异或同时从位选择电路7输出的位数据的所有比特的操作，并将一位的运算结果输出到移位寄存器9.这使得可以高速执行卷积码处理。

7. 发明授权

US06477678B1 Method and device for error correcting coding for high rate digital data transmissions, and corresponding decoding method and device 有权
标题翻译：用于对高速数字数据传输进行纠错编码的方法和装置及相应的解码方法和装置
公开(公告)号：US06477678B1
公开(公告)日：2002-11-05
申请号：US09446517
申请日：1999-12-28
申请人： Juing Fang , Vincent Lemaire
发明人： Juing Fang , Vincent Lemaire
IPC分类号： H03M1323
CPC分类号： H03M13/6561 , H03M13/2936 , H03M13/43
摘要： It is proposed to use channel coding involving a plurality of concatenated coders and decoders in series and in parallel for coded transmission in which the efficiency can be adapted as a function of the requirements of a system and an application. The coders of the invention are convolutional self-orthogonal code (CSOC) coders. It is shown that this enables perfect adaptation with circuits whose complexity and cost are low and which therefore support high bit rates.
摘要翻译：建议使用涉及多个级联编码器和解码器的信道编码，并行编码传输，其中效率可以根据系统和应用的要求进行调整。本发明的编码器是卷积自正交码（CSOC）编码器。这表明，这使得能够与复杂性和成本低的电路完美适应，并因此支持高比特率。

8. 发明授权

US06467064B1 Viterbi decoder 失效
标题翻译：维特比解码器
公开(公告)号：US06467064B1
公开(公告)日：2002-10-15
申请号：US09464210
申请日：1999-12-15
申请人： Taizo Anan , Akira Nakagawa , Eishi Morimatsu
发明人： Taizo Anan , Akira Nakagawa , Eishi Morimatsu
IPC分类号： H03M1323
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/6505
摘要： A Viterbi decoder for decoding a receive signal series encoded by an error correcting code is disclosed. The Viterbi decoder comprises a storage unit for storing a plurality of branch metrics, and a control unit for performing, upon receipt of the receive signal series, the processing of selecting a surviving path for each status using the branch metrics stored in the storage unit. The memory is prepared in accordance with the pattern of the receive signal series for storing a plurality of tables holding the branch metrics corresponding to each status. Each table holds the branch metrics in such a manner that the branch metrics of the two branches entering each status may be read by the control unit in the order of the branches constituting a trellis.
摘要翻译：公开了一种用于对由纠错码编码的接收信号序列进行解码的维特比解码器。维特比解码器包括用于存储多个分支度量的存储单元，以及控制单元，用于在接收到接收信号序列时，使用存储在存储单元中的分支度量来选择用于每个状态的存活路径的处理。存储器根据用于存储保持与每个状态对应的分支度量的多个表的接收信号序列的模式来准备。每个表保持分支度量，使得进入每个状态的两个分支的分支度量可以由控制单元以构成网格的分支的顺序读取。

9. 发明授权

US06307901B1 Turbo decoder with decision feedback equalization 有权
标题翻译：具有判决反馈均衡的Turbo解码器
公开(公告)号：US06307901B1
公开(公告)日：2001-10-23
申请号：US09563064
申请日：2000-04-24
申请人： Xiaoyong Yu , Ming Tan , Mang Zhu
发明人： Xiaoyong Yu , Ming Tan , Mang Zhu
IPC分类号： H03M1323
CPC分类号： H04L1/005 , H03M13/2957 , H03M13/3905 , H03M13/6331 , H04L1/0066 , H04L1/0068 , H04L25/03057
摘要： A decoder equalizes a turbo coded signal with intersymbol interference by performing a decision-feedback equalization in each iteration of the turbo decoding process. In such iteration process, two recursion processors calculate soft output values for the information bits and the coded bits of the signal as well. Hard output values are derived from the soft output values. A decision feedback equalizer in an iterative loop of the decoder receives the hard output values uses these to provide a correction for the intersymbol interference. Thereafter, the decision feedback signal applies the correction signal to the input signal to minimize the intersymbol interference.
摘要翻译：解码器通过在turbo解码过程的每次迭代中执行判决反馈均衡来均衡turbo编码信号与符号间干扰。在这种迭代过程中，两个递归处理器也计算信息位的软输出值和信号的编码位。硬输出值来自软输出值。解码器的迭代循环中的判决反馈均衡器接收硬输出值，使用这些值来提供符号间干扰的校正。此后，判决反馈信号将校正信号施加到输入信号以最小化符号间干扰。

10. 发明授权

US06192501B1 High data rate maximum a posteriori decoder for segmented trellis code words 失效
标题翻译：高数据速率最大后验解码器，用于分段网格码字
公开(公告)号：US06192501B1
公开(公告)日：2001-02-20
申请号：US09137181
申请日：1998-08-20
申请人： Stephen Michael Hladik , Nick Andrew Van Stralen , John Anderson Fergus Ross
发明人： Stephen Michael Hladik , Nick Andrew Van Stralen , John Anderson Fergus Ross
IPC分类号： H03M1323
CPC分类号： H03M13/3905 , H03M13/27 , H03M13/2993 , H03M13/3972
摘要： In a communications system, a trellis code word is segmented by both the encoder and a segmented MAP decoder. The segmented MAP decoder operates on code word segments as if they were individual code words and takes advantage of knowing the state of the encoder at specified times to reduce decoding latency and required memory. In a turbo coding system, for example, coding gain is maintained by interleaving the information bits across the segments of a component code word.
摘要翻译：在通信系统中，网格码字由编码器和分段MAP解码器分段。分段MAP解码器对代码字段进行操作，就像它们是单独的代码字，并且利用在指定时间知道编码器的状态来减少解码延迟和所需的存储器。在turbo编码系统中，例如，通过在分量码字的片段之间交织信息比特来维持编码增益。

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