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1. 发明专利

JPS4939318B1 失效
公开(公告)号：JPS4939318B1
公开(公告)日：1974-10-24
申请号：JP7129966
申请日：1966-10-27
IPC分类号： H01L31/14 , H01L17/00

2. 发明专利

JPS4937302B1 失效
公开(公告)号：JPS4937302B1
公开(公告)日：1974-10-08
申请号：JP6516865
申请日：1965-10-20
IPC分类号： H01L21/203 , H01L17/00 , B01J17/28

3. 发明专利

JPS4931596B1 失效
公开(公告)号：JPS4931596B1
公开(公告)日：1974-08-22
申请号：JP7129266
申请日：1966-10-27
IPC分类号： H01L31/14 , H01L17/00

4. 发明专利

JPS4813277B1 失效
公开(公告)号：JPS4813277B1
公开(公告)日：1973-04-26
申请号：JP682468
申请日：1968-02-02
IPC分类号： H05B33/10 , G03G5/02 , G03G5/043 , G03G5/14 , H01L17/00

5. 发明专利

JPS4931600B1 失效
公开(公告)号：JPS4931600B1
公开(公告)日：1974-08-22
申请号：JP7129666
申请日：1966-10-27
IPC分类号： G09F13/22 , H01L31/14 , H05B33/00 , H01L17/00

6. 发明专利

JPS4931595B1 失效
公开(公告)号：JPS4931595B1
公开(公告)日：1974-08-22
申请号：JP2084867
申请日：1967-03-31
IPC分类号： H01L31/14 , H05B33/12 , H01L17/00

7. 发明授权

US4257825A Method of manufacturing semiconductor devices having improvements in device reliability by thermally treating selectively implanted test figures in wafers 失效
标题翻译：通过对晶片中的选择性地植入的测试图进行热处理来制造具有设备可靠性提高的半导体器件的方法
公开(公告)号：US4257825A
公开(公告)日：1981-03-24
申请号：US63314
申请日：1979-08-02
申请人： Hanno Schaumburg
发明人： Hanno Schaumburg
IPC分类号： G01R31/27 , G01R31/302 , G01R31/308 , H01L21/263 , H01L21/265 , H01L21/268 , H01L21/66 , H01L21/26 , G01R31/22 , H01L17/00
CPC分类号： H01L22/20 , G01R31/275 , G01R31/302 , G01R31/308 , H01L21/2636 , H01L21/265 , H01L21/268
摘要： A method of manufacturing semiconductor devices in which at least one zone is formed in a number of semiconductor wafers by implantation of doping ions and by a subsequent thermal treatment. In order to reduce the costs for the thermal treatment (individual test wafers) and to reduce the spread, at least one test figure is formed in each semiconductor wafer by the implantation and is subjected to a thermal treatment after the implantation of the doping ions by means of an intensive radiation directed thereon. The electrical properties of the test figure are then measured and further thermal treatment of the whole semiconductor wafer is determined in accordance with the result of this measurement.
摘要翻译：一种制造半导体器件的方法，其中通过注入掺杂离子在多个半导体晶片中形成至少一个区域，以及随后的热处理。为了降低热处理（单个测试晶片）的成本并减少扩散，通过注入在每个半导体晶片中形成至少一个测试图，并且在掺杂离子注入之后进行热处理指向其上的集中辐射的手段。然后测量测试图的电性能，并根据该测量的结果确定整个半导体晶片的进一步热处理。

8. 发明授权

US3829883A Magnetic field detector employing plural drain igfet 失效
标题翻译：使用全面排水IGFET的磁场探测器
公开(公告)号：US3829883A
公开(公告)日：1974-08-13
申请号：US41457073
申请日：1973-11-09
申请人： BATE R
发明人： BATE R
IPC分类号： G01R33/06 , H01L29/82 , H01L17/00
CPC分类号： G01R33/06 , H01L29/82
摘要： A mode of operation of a three-drain configured insulated gate field effect transistor which is extremely sensitive to magnetic fields is disclosed. The gate of the transistor is biased to a level less than transistor threshold, or alternatively, is connected to substrate ground. A first drain region opposite the source is biased to achieve avalanche breakdown of the junction. The other two drains are defined on either side of a line joining the source and first drain. These two drains are biased at a voltage below that required for avalanche of their junctions. In response to a magnetic field a voltage difference is generated across these two drains. In one embodiment of the invention, the region opposite the source is of a conductivity type the same as the substrate. In this configuration the detector does not require avalanche breakdown.
摘要翻译：公开了对磁场非常敏感的三漏配置绝缘栅场效应晶体管的工作模式。晶体管的栅极被偏置到小于晶体管阈值的电平，或者替代地，连接到衬底接地。与源极相对的第一漏极区域被偏置以实现结的雪崩击穿。另外两个排水口被限定在连接源和第一排水管的两侧。这两个排水管的偏压低于其路口雪崩所需的电压。响应于磁场，跨这两个排水口产生电压差。在本发明的一个实施例中，与源极相对的区域的导电类型与衬底相同。在这种配置下，探测器不需要雪崩击穿。

9. 发明授权

US3823354A Hall element 失效
标题翻译：霍尔元素
公开(公告)号：US3823354A
公开(公告)日：1974-07-09
申请号：US36489273
申请日：1973-05-29
申请人： PHILIPS CORP
发明人： JANSSEN J
IPC分类号： H01L27/22 , H01L43/06 , H01L17/00
CPC分类号： H01L27/22 , H01L43/065
摘要： The invention relates to a semiconductor device having a Hall element. In order to reduce the offset voltage between the connection contacts for deriving the Hall signals and in order to increase the stability, the Hall element shows a number of subHall elements which are arranged parallel to each other. The Hall bodies of the sub-Hall elements, viewed on the surface of the semiconductor body, are situated beside each other in the semiconductor body and show different directions of current. The semiconductor body may be constituted by an epitaxial layer of ntype silicon on a substrate of p-type silicon. The Hall element may be manufactured by using methods which are generally known in manufacturing integrated circuits.

10. 发明授权

US3810301A Method for making an integrated circuit apparatus 失效
标题翻译：制造集成电路设备的方法
公开(公告)号：US3810301A
公开(公告)日：1974-05-14
申请号：US28549672
申请日：1972-08-31
申请人： RECH IND DU QUEBUE CENTRE
发明人： COOK R
IPC分类号： H01L21/82 , G11C29/00 , G11C29/28 , H01L23/525 , H01L17/00
CPC分类号： H01L23/5256 , G11C29/006 , G11C29/28 , H01L2924/0002 , Y10T29/49004 , H01L2924/00
摘要： The method consists in subdividing an entire substrate into many independent and identical circuit arrays with each array containing an identical programmable section, in programming the first array to respond to a certain set of electrical impulses, in testing the array for electrical function: if the array is good, proceeding with the programming and testing of the programmable section of the second array using another set of electrical impulses; if the array is faulty, proceeding with the programming and testing of the programmable section of the second array with the same set of electrical impulses used for the previous faulty array; then, repeating the above programming and testing steps for the remaining circuit arrays of the substrate using different sets of electrical impulses; and then establishing connection between the system connect lines of each array.
摘要翻译：该方法包括将整个基板细分成许多独立且相同的电路阵列，每个阵列包含相同的可编程部分，在编程第一阵列以响应某组电脉冲时，在测试阵列中进行电功能：如果阵列是良好的，继续使用另一组电脉冲编程和测试第二阵列的可编程部分; 如果阵列有故障，则使用与先前故障阵列相同的电脉冲集进行第二阵列的可编程部分的编程和测试; 然后，使用不同组的电脉冲重复上述用于衬底的剩余电路阵列的编程和测试步骤; 然后在每个阵列的系统连接线之间建立连接。

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