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1. 发明专利

IL185127D0 PROCESSING INFORMATION MANAGEMENT IN A PLASMA PROCESSING TOOL 未知
公开(公告)号：IL185127D0
公开(公告)日：2007-12-03
申请号：IL18512707
申请日：2007-08-08
申请人： LAM RES CORP , CHAD R WEETMAN , CHUNG HO HUANG , JACQUELINE SETO , JOHN JENSEN
IPC分类号： G11C20100101
摘要： A plasma-processing tool for processing a substrate using at least a first process recipe and a second process recipe is provided. The plasma-processing tool includes transducers configured to collect process data streams, each process data stream pertaining to a process parameter being monitored during recipe execution. The tool also includes a logic circuitry configured for receiving a set of meta-data wherein each meta-data includes identification data about the substrate and the process recipe being executed. The logic circuitry is also configured for receiving a set of process data streams, each of which being associated with a specific process recipe. The logic circuitry further includes storing the meta-data and the process data streams associated with the first process recipe as a first file and the meta-data and the process data streams associated with the second process recipe as a second file.

2. 发明专利

IL184105D0 ERASED SECTOR DETECTION MECHANISMS 未知
公开(公告)号：IL184105D0
公开(公告)日：2007-10-31
申请号：IL18410507
申请日：2007-06-21
申请人： SANDISK CORP
IPC分类号： G11C20100101
摘要： The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still be used as the number of corrupted bits is under the ECC correction limit. This method allows the storage system to become tolerant to erased sectors corruption, as such sectors can be used for further data storage if the system can correct this error later in the written data by ECC correction means.

3. 发明专利

IL184020D0 DIRECTED AUTO-REFRESH SYNCHRONIZATION 未知
公开(公告)号：IL184020D0
公开(公告)日：2007-10-31
申请号：IL18402007
申请日：2007-06-18
申请人： QUALCOMM INC
IPC分类号： G11C20100101
摘要： In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory Module. A bank address counter internal to the memory is initialized to a first pre-determined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second pre-determined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.

4. 发明专利

IL183416D0 METHOD AND SYSTEM FOR MINIMIZING IMPACT OF REFRESH OPERATION ON VOLATILE MEMORY PERFORMANCE 未知
公开(公告)号：IL183416D0
公开(公告)日：2007-09-20
申请号：IL18341607
申请日：2007-05-24
申请人： QUALCOMM INC
IPC分类号： G11C20100101
摘要： A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.

5. 发明专利

IL182076D0 IN VIVO DEVICE FOR ASSISTING AND IMPROVING DIASTOLIC VENTRICULAR FUNCTION 未知
公开(公告)号：IL182076D0
公开(公告)日：2007-07-24
申请号：IL18207607
申请日：2007-03-20
申请人： CORASSIST CARDIOVASCULAR LTD
IPC分类号： G11C20100101

6. 发明专利

IL181245D0 REGISTER FILE APPARATUS AND METHOD INCORPORATING READ-AFTER-WRITE BLOCKING USING DETECTION CELLS 未知
公开(公告)号：IL181245D0
公开(公告)日：2007-07-04
申请号：IL18124507
申请日：2007-02-08
申请人： IBM
IPC分类号： G11C20100101
摘要： A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

9. 发明专利

IL196239D0 METHOD OF ERROR CORRECTION IN A MULTI-BIT-PER-CELL FLASH MEMORY 未知
公开(公告)号：IL196239D0
公开(公告)日：2009-09-22
申请号：IL19623908
申请日：2008-12-28
申请人： UNIV RAMOT , ALROD IDAN , LITSYN SIMON , SHARON ERAN
IPC分类号： G11C20100101

10. 发明专利

IL187864D0 METHODS AND APPARATUS FOR READING A FULL-SWING MEMORY ARRAY 未知
公开(公告)号：IL187864D0
公开(公告)日：2008-03-20
申请号：IL18786407
申请日：2007-12-03
申请人： QUALCOMM INC
IPC分类号： G11C20100101
摘要： Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines (240A,240B) and a global bit line (253). In order to reduce power consumption, a method of driving the global bit line (253) includes the step of coupling the plurality of local bit lines (240A,240B) to the global bit line (253) through a plurality of tri-state devices (255). The method further includes the steps of generating a global select signal (250) to enable one of the plurality of tri-state devices (255) and selecting a corresponding local bit line (240A,240B) to drive the output of the enabled tri-state device (255). In this way, the global bit line (253) is statically driven so that consecutive reads of bits having the same value read over the global bit line (253) do not result in transitioning the state of the global bit line (253).

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