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1. 发明申请

US20040133825A1 Path delay measuring circuitry 审中-公开
标题翻译：路径延迟测量电路
公开(公告)号：US20040133825A1
公开(公告)日：2004-07-08
申请号：US10698532
申请日：2003-11-03
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
发明人： Takuya Kobayashi
IPC分类号： G01R001/00 , G11B005/00 , G06K005/04 , G11B020/20
CPC分类号： G01R31/318328
摘要： A path delay measuring circuitry includes a pattern creating circuit 105 for creating a test pattern to be supplied to a combination circuit 101, a comparison/decision circuit 106 for comparing an output from the combination circuit and an expected value, a clock creating circuit 301 for creating a clock with a variable clock interval while a capturing operation is carried out according to a clock mode value, and a timing signal creating circuit 107 for supplying an operation timing signal to each of the respective circuits. The clock generating circuit 301 includes a clock mode counter for producing a clock mode value which is updated whenever a decision for signal transition time is made.
摘要翻译：路径延迟测量电路包括用于产生要提供给组合电路101的测试图案的模式产生电路105，用于比较组合电路的输出和预期值的比较/判定电路106，用于在根据时钟模式值执行捕获操作的同时创建具有可变时钟间隔的时钟;以及定时信号产生电路107，用于向各个电路提供操作定时信号。时钟发生电路301包括用于产生时钟模式值的时钟模式计数器，每当进行用于信号转换时间的决定时，时钟模式值被更新。

2. 发明申请

US20040128590A1 Patch mechanism 审中-公开
标题翻译：补丁机制
公开(公告)号：US20040128590A1
公开(公告)日：2004-07-01
申请号：US10334231
申请日：2002-12-30
发明人： Michael Derr
IPC分类号： G11B005/00 , G06K005/04 , G11B020/20 , G06F011/00
CPC分类号： G06F11/0793 , G06F9/328 , G06F11/0721
摘要： Embodiments of the present invention provide a patch device that can be programmed by software to detect and repair a wide range of conditions. In particular, patch device includes trigger-matching logic, programmable buffer for holding a patch sequence, and control logic to block the triggering sequence and perform the patch sequence. Once programmed and enabled by software, the input stimulus (for example, incoming cycles) are compared with the programmed trigger registers. When a match is detected, the control logic replaces and/or modifies the sampled cycle(s) with the sequence of instructions in the patch buffer. The modified sequence avoids or corrects the condition.
摘要翻译：本发明的实施例提供一种补丁装置，其可由软件编程以检测和修复各种各样的条件。特别地，补丁设备包括触发匹配逻辑，用于保存补丁序列的可编程缓冲器以及阻塞触发序列并执行补丁序列的控制逻辑。一旦通过软件编程和使能，输入激励（例如，进入周期）与编程的触发寄存器进行比较。当检测到匹配时，控制逻辑用补丁缓冲器中的指令序列替换和/或修改采样周期。修改的序列避免或纠正条件。

3. 发明申请

US20040049718A1 Transponder interrogators, radio frequency identification device communication systems, transponder interrogator communication methods, and radio frequency identification device communication methods 失效
标题翻译：应答器询问器，射频识别设备通信系统，应答器询问器通信方法和射频识别设备通信方法
公开(公告)号：US20040049718A1
公开(公告)日：2004-03-11
申请号：US10655653
申请日：2003-09-05
发明人： George E. Pax , David K. Ovard
IPC分类号： G11B005/00 , G06K005/04 , G11B020/20
CPC分类号： H04L7/0334 , G06K7/0008 , G06K19/0723 , H03M13/33 , H04L7/046 , H04L7/10
摘要： The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.
摘要翻译：本发明包括位同步器和同步和计算误差的方法。根据本发明的与数据信号同步的一种方法包括提供具有第一部分和第二部分的数据信号，产生定时信号，首先在数据信号的第一部分调整定时信号，累积历史数据信号的第一部分期间的值，并且在使用历史的数据信号的第二部分期间第二调整定时信号。

4. 发明申请

US20030204793A1 Method and apparatus for measuring data timing using unity time-voltage sawtooth ramps 失效
标题翻译：使用单位时间 - 电压锯齿波形测量数据定时的方法和装置
公开(公告)号：US20030204793A1
公开(公告)日：2003-10-30
申请号：US10134390
申请日：2002-04-30
发明人： Richard I. Mellitz
IPC分类号： G11B005/00 , G06K005/04 , G11B020/20
CPC分类号： G01R29/26
摘要： A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.
摘要翻译：一种用于将接收信号中的偏斜转换为低频电压的方法和装置。从源节点的原始信号在目的地节点处接收信号。在目的地节点处创建一个统一的时间锯齿波斜坡信号。单位时间 - 电压锯齿波斜波信号的幅度是与原始信号的脉冲宽度值成比例的电压值。单位时间电压锯齿波信号在接收信号开始之前开始。从单位时间 - 电压锯齿波斜坡信号的开始到接收信号的边沿上的阈值电平测量偏斜时间。测量的偏斜时间与单位时间 - 电压锯齿波形上的电压电平相关。每个边沿的测量的偏斜时间被转换成脉冲，其中每个脉冲的电压电平与测量的偏差成比例。

5. 发明申请

US20030135796A1 Variable delay circuit 失效
公开(公告)号：US20030135796A1
公开(公告)日：2003-07-17
申请号：US10379261
申请日：2003-03-04
发明人： Toshiyuki Okayasu
IPC分类号： G11B005/00 , G06K005/04 , G11B020/20
CPC分类号： H03K5/133 , H03K2005/00032 , H03K2005/00058 , H03K2005/00071 , H03K2005/00195
摘要： A variable delay circuit comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements, according to a number of the first variable delay elements; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.

6. 发明申请

US20030091136A1 Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method 失效
标题翻译：倾斜调整电路，偏移调整方法，数据同步电路和数据同步方法
公开(公告)号：US20030091136A1
公开(公告)日：2003-05-15
申请号：US10164374
申请日：2002-06-10
申请人： Seiko Epson Corporation
发明人： Natsuki Sugita
IPC分类号： H04L007/00 , G11B005/00
CPC分类号： H04L7/0338 , H04L7/046 , H04L25/14
摘要： A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a T.M.D.S. link in accordance with the DVI standard. The skew adjustment circuit includes a sampling point selection section that performs comparison processing on oversampled data, assumes transition points of serial data, and outputs a sampling point selection signal; and a data recovery section that outputs oversampled data at the sampling point selected by the selection signal, as sample data for the serial data. Comparison processing is performed on the oversampled data in 4-bit segment units of the serial data, transition point detection signals are held, and the transition points of the serial data are assumed based on those transition point detection signals, when transition point detection signals for at least two segments, which are among the held transition point detection signals, indicate the same result. The comparison processing is performed on next-but-one pairs of oversampled data.
摘要翻译：偏斜调整电路采用一种新颖的算法，能够减小T.M.D.S.的接收机的电路的电平。按照DVI标准链接。偏斜调整电路包括对过采样数据执行比较处理的采样点选择部分，假设串行数据的转换点，并输出采样点选择信号; 以及数据恢复部，其在由选择信号选择的采样点处输出过采样数据作为串行数据的采样数据。对串行数据的4位段单位的过采样数据执行比较处理，保持转换点检测信号，并且基于这些转变点检测信号假设串行数据的转换点，当转移点检测信号为在保持的转变点检测信号之中的至少两个段表示相同的结果。比较处理是对一对过采样数据执行的。

7. 发明申请

US20030044170A1 Digital video recorder using circular file management and method of operation 有权
标题翻译：数字录像机使用循环文件管理和操作方法
公开(公告)号：US20030044170A1
公开(公告)日：2003-03-06
申请号：US09943791
申请日：2001-08-31
发明人： Semir S. Haddad , Michael J. Jones
IPC分类号： H04N005/781 , G11B005/00
CPC分类号： H04N5/76 , H04N5/781 , H04N5/85 , H04N9/8042
摘要： There is disclosed a digital video recorder that uses a circular file management system to efficiently manage time-shifted viewing a live video broadcast television program. There is provided for use in the digital video recorder, an apparatus for performing time-shifted viewing of an incoming television program being received by the digital video recorder. The apparatus comprises a controller capable of creating a data file having a defined maximum size on a storage disk of the digital video recorder and capable of causing video data associated with the incoming television program to be stored sequentially in the data file from a first location to an Nth location. The controller, in response to a determination that the video data has been stored in the Nth location, causes a next received video data to be stored in the first location.
摘要翻译：公开了一种使用循环文件管理系统来有效地管理实时视频广播电视节目的时移观看的数字视频记录器。提供用于数字视频记录器的装置，用于对由数字录像机接收的输入电视节目进行时移观看的装置。该装置包括能够在数字视频记录器的存储盘上创建具有限定的最大尺寸的数据文件的控制器，并且能够将与输入的电视节目相关联的视频数据顺序地存储在数据文件中，从第一位置到第N个位置。控制器响应于确定视频数据已经存储在第N个位置，导致下一个接收到的视频数据被存储在第一位置。

8. 发明申请

US20030043488A1 Methods and apparatus for increased magnetic coding density by precise placement of magnetic transitions 有权
公开(公告)号：US20030043488A1
公开(公告)日：2003-03-06
申请号：US10281656
申请日：2002-10-28
申请人： XTec, Incorporated
发明人： Alberto J. Fernandez , Carlos D. Bormey , Ismael E. Negrin
IPC分类号： G11B005/00 , G11B015/12 , G11B020/10
CPC分类号： G06K19/06187 , G06K1/125 , G06K7/084 , G06K19/12
摘要： Methods and apparatus for increasing the density of data storage on a magnetic medium by using variations in positioning of magnetic transitions to encode bits. Conventionally encoded bits are written to the medium as sequences of magnetic transitions according to an encoding standard. Additional bits are encoded on the medium as deviations from a nominal position of magnetic transitions separating conventionally encoded bits. The deviation from the nominal position is within an allowable range of tolerance for the standard followed in encoding the conventionally encoded bits. In order to prevent accumulation of error, additional bits are only encoded in transitions separating a pair of conventionally encoded bits. The first and last transitions of the pair do not have additional bits encoded as deviations of transition locations. This technique allows the encoding of one additional bit for every two conventionally encoded bits.

9. 发明申请

US20030041292A1 Data recovery circuit for minimizing power consumption by non-integer times oversampling 失效
公开(公告)号：US20030041292A1
公开(公告)日：2003-02-27
申请号：US10193051
申请日：2002-07-11
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-Kug Lee , Yong-Sub Kim , Gun-Sang Lee
IPC分类号： G11B005/00 , G06K005/04 , G11B020/20
CPC分类号： H04L7/0338 , G11B20/1426
摘要： A data recovery circuit and method for minimizing errors due to clock skew at a lower power are provided. The data recovery circuit includes a phase-locked loop, an oversampling unit, a pattern detector, a state selector, and a data selector. The data recovery circuit has a phase-locked loop for generating a plurality of clock signals, each of which is synchronized to an input clock signal and has a different delay time; an oversampling unit for non-integer times oversampling serial data which is input from the outside, in response to the plurality of clock signals, and outputting the oversampled result as sample data formed of a plurality of bits; a pattern detector for receiving the sample data formed of the plurality of bits, and generating a pattern signal formed of a plurality of bits by detecting level transitions between bits of the sample data; a state accumulator for receiving the pattern signal formed of the plurality of bits, accumulating the frequency of occurrence of the pattern signal, and outputting the pattern signal having the highest frequency of occurrence as a state signal formed of a plurality of bits; a state selector for receiving the state signal formed of the plurality of bits, and generating a state selection signal formed of a plurality of bits for selecting bits at predetermined positions in the sample data; and a data selector for receiving the sample data, selecting bits of the sample data in response to the state selection signal, where the bits correspond to the state selection signal, and outputting the selected bits as recovered data formed of a plurality of bits. The oversampling unit has a plurality of sampling means, each for receiving the serial data, sampling the serial data in response to each of the plurality of clock signals, and then outputting one bit of the sample data. The oversampling unit 2.7 times oversamples each one bit section of the input serial data. According to the data recovery circuit and method, the clock frequency of a phase-locked loop for recovering data having the same frequency is set at a lower level, and therefore power consumption is minimized.

10. 发明申请

US20020071656A1 REWIND RADIO AND TELEVISION 有权
标题翻译： REWIND无线电和电视
公开(公告)号：US20020071656A1
公开(公告)日：2002-06-13
申请号：US09143343
申请日：1998-08-28
发明人： MARK A. BOYS
IPC分类号： H04N005/783 , G11B005/00 , H04N005/781
CPC分类号： H04N5/76 , G11B27/024 , G11B27/028 , G11B27/031 , G11B27/034 , G11B27/28 , G11B2220/41 , G11B2220/455 , G11B2220/61 , G11B2220/90 , G11B2220/91
摘要： A radio or television apparatus has tuning circuitry for selecting a channel from an input spectrum, an output for presenting a presentation from a selected channel, a recording apparatus having a memory with capacity for recording a fixed time duration T of the selected presentation, and adapted to make an audio record sequentially in a circular fashion, such that when the memory capacity is filled, the device continues to record, overwriting the oldest recorded information, providing thereby, at any point in time, a stored copy of time duration T immediately preceding the point in time. This innovation provides limited rewind capability for real-time data streams. In alternative embodiments add-on devices are provided for existing radios and TVs.
摘要翻译：无线电或电视设备具有用于从输入频谱中选择频道的调谐电路，用于呈现来自所选频道的呈现的输出，具有用于记录所选择的演示文稿的固定持续时间T的能力的存储器的记录装置，以循环方式顺序地进行音频记录，使得当存储器容量被填充时，设备继续记录，重写最旧的记录信息，从而在任何时间点提供紧接在前面的持续时间T的存储副本时间点该创新为实时数据流提供了有限的倒带能力。在替代实施例中，为现有的无线电和电视提供附加设备。

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