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1. 发明申请

WO2023278176A1 WORK QUEUE FOR COMMUNICATION BETWEEN A PRODUCER AND A CONSUMER 审中-公开
公开(公告)号：WO2023278176A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/033907
申请日：2022-06-17
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： DRAGOJEVIC, Aleksandar , LIU, Junyi
IPC分类号： G06F9/54 , G06F2209/548 , G06F9/544
摘要： A system comprising: a producer of work items, a circular buffer for queueing the items, and a consumer of the items. Each slot in the buffer comprises a descriptor field and a sequence number field. The buffer also comprises a head field specifying the sequence number of the head slot, and a tail field specifying the sequence number of the tail slot. To enqueue a new item, the producer increments the tail field, and writes the new item to the slot that was the tail slot prior to the increment. The consumer tracks a next expected sequence number based on how many items it has consumed so far. To consume a next item from the work queue, the consumer polls the sequence number of the head slot to check whether it equals the expected sequence number, and on condition thereof consumes the next work item.

2. 发明申请

WO2021148461A1 A SYSTEM AND A METHOD FOR SECURE DATA TRANSFER USING AIR GAPPING HARDWARE PROTOCOL 审中-公开
公开(公告)号：WO2021148461A1
公开(公告)日：2021-07-29
申请号：PCT/EP2021/051188
申请日：2021-01-20
申请人： FUNDACJA "BLOCKCHAIN DEVELOPMENT FOUNDATION"
发明人： GANCARZ, Kamil Rafal
IPC分类号： H04L29/06 , H04B1/44 , G06F21/85 , G06F13/4022 , G06F21/72 , G06F9/544 , H04L63/0209 , H04L63/0442 , H04L63/0471 , H04L9/006 , H04L9/0825 , H04L9/083 , H04L9/3213 , H04L9/3247
摘要： A system for secure data transfer using air gapping. A first module (100) comprises: a first module communication interface (102) configured to communicate with a public network; a first module controller (105) and a first module data interface (106) configured send and/or receive data from the public network. A second module (200) comprises: a first read-only memory (202) storing an operating system; a second module communication interface (208) configured to communicate with a secured machine or a secured network to transmit data from and to the second module; a microcontroller (205) and a second module data interface (206, 207) for communicating with a bridge module (300). The bridge module (300) comprises: a bridge module controller (305); a bridge module data interface (309) for communicating with the bridge module controller (305); memory (303) for storing data; a switch (310) configured to selectively connect the bridge module data interface (309) to either the first module data interface (106) or to the second module data interface (206, 207) such that the first module data interface (106) is never connected with the second module data interface (206, 207). The bridge module controller (305) is configured to receive data from the second module (200), store the data in the memory (303), and send the data to the first module (100) and/or to receive data from the first module (100), store the data in the memory (303), and send the data to the second module (200). The second module (200) further comprises a second read-only memory (203) storing sets of private keys of the second module (200) and at least one public key of another remote entity; a cryptographic unit (209) configured to encrypt and/or decrypt data using the keys stored in the second read-only memory (203).

3. 发明申请

WO2021190828A1 ACCELERATING COMPUTATIONS IN A PROCESSOR 审中-公开
公开(公告)号：WO2021190828A1
公开(公告)日：2021-09-30
申请号：PCT/EP2021/053934
申请日：2021-02-18
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： HESSLER, Martin , WIBERG, Niclas
IPC分类号： G06F17/14 , G06F9/50 , G06F9/54 , G06F17/142 , G06F9/5066 , G06F9/544
摘要： A method for accelerating computations in a processor comprising one or more processing units, wherein one or more threads of execution are associated with one or more processing elements and with a shared memory of the one or more processing units for performing computations by parallel execution of the one or more threads is disclosed. The method comprises performing computations (102) by parallel execution of the one or more threads in the one or more processing elements by using the shared memory, wherein the one or more threads are synchronized by: determining (102a) dependent computations of the one or more threads in a warp, wherein the warp comprises a pre-determined number of threads, mapping (102b) adjacent entries of a fast Fourier transform to respective threads of the determined dependent computations of the warp, exchanging data (102d) between the one or more respective threads, and performing (102e) the determined dependent computations of the respective threads based on exchanged data between the one or more respective threads. Corresponding computer program product, apparatus, and processor are also disclosed.

4. 发明申请

WO2021126839A1 METHODS AND APPARATUS TO FACILITATE SPECULATIVE PAGE FAULT HANDLING IN A GRAPHICS PROCESSING UNIT 审中-公开
公开(公告)号：WO2021126839A1
公开(公告)日：2021-06-24
申请号：PCT/US2020/065101
申请日：2020-12-15
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Andrew Evan
IPC分类号： G06F12/0862 , G06F9/38 , G06T1/60 , G06F11/0772 , G06F11/0793 , G06F12/0871 , G06F12/0882 , G06F2212/1024 , G06F2212/6028 , G06F9/30047 , G06F9/3861 , G06F9/5016 , G06F9/5022 , G06F9/544
摘要： The present disclosure relates to methods and apparatus for display processing. For example, disclosed techniques facilitate speculative page fault handling in a GPU. Aspects of the present disclosure can perform a graphics operation associated with using a set of constants within a flow control. Aspects of the present disclosure can also query a first memory to determine whether memory addresses associated with the set of constants are allocated at a constant buffer of the first memory. Further, aspects of the present disclosure can set a page fault indicator to a true value when the query indicates that at least one memory address associated with the set of constants is unallocated at the constant buffer, and set the page fault indicator to a false value otherwise.

5. 发明申请

WO2020164991A8 VERFAHREN ZUM ÜBERTRAGEN EINER NACHRICHT IN EINEM RECHENSYSTEM SOWIE RECHENSYSTEM 审中-公开
公开(公告)号：WO2020164991A8
公开(公告)日：2020-08-20
申请号：PCT/EP2020/052855
申请日：2020-02-05
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： GRAF, Rene
IPC分类号： G06F9/54 , G06F9/544 , G06F9/546
摘要： Die Erfindung betrifft ein Verfahren zum Übertragen einer Nachricht in einem Rechensystem (1) mit den Schritten: Senden der Nachricht mit einem Sender (S) und Empfangen der Nachricht mit einem Empfänger (E), wobei dem Sender (S) zum Senden ein Zugriff auf einen Speicherbereich (2) erteilt wird, dem Sender (S) nach dem Senden der Zugriff auf den Speicherbereich (2) entzogen wird und anschließend dem Empfänger (E) zum Empfangen der Zugriff auf den Speicherbereich (2) erteilt wird und wobei dem Sender (S) für den Zugriff auf den Speicherbereich (2) eine erste virtuelle Adresse (P1) zugewiesen wird und dem Empfänger (E) für den Zugriff auf den Speicherbereich (2) eine zweite virtuelle Adresse (P2) zugewiesen wird, wobei sich die erste virtuelle Adresse (P1) von der zweiten virtuellen Adresse (P2) unterscheidet.

6. 发明申请

WO2023273025A1 任务处理系统、电子设备和存储介质审中-公开
公开(公告)号：WO2023273025A1
公开(公告)日：2023-01-05
申请号：PCT/CN2021/125004
申请日：2021-10-20
申请人：上海商汤科技开发有限公司
发明人：肖波
IPC分类号： G06F9/50 , G06F18/214 , G06F2209/547 , G06F2209/548 , G06F9/5022 , G06F9/5027 , G06F9/542 , G06F9/544 , G06F9/546 , G06F9/547
摘要：提供了一种任务处理系统、电子设备和存储介质。系统包括至少一个处理器，处理器用于运行管理进程（101）、中间进程（102）及执行进程（103），管理进程用于在处理预设任务期间管理中间进程及执行进程，中间进程用于创建执行进程，执行进程用于执行预设任务的子任务，管理进程被配置为：在存在待执行的子任务的情况下，检测中间进程是否已创建；在中间进程已创建的情况下，向中间进程发送针对子任务的进程创建请求；中间进程被配置为：响应于管理进程发送的进程创建请求，创建执行进程；执行进程被配置为：执行子任务，得到子任务的执行结果；向管理进程发送子任务的执行结果。

7. 发明申请

WO2022241168A1 PERFORMING MATRIX VALUE INDICATION 审中-公开
公开(公告)号：WO2022241168A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/029075
申请日：2022-05-12
申请人： NVIDIA CORPORATION
发明人： SHIN, Jaewook , ATUKURI, Balaji Krishna Yugandhar , GORNISH, Edward H. , VENKATESH, Jayashree
IPC分类号： G06F9/30 , G06F7/544 , G06F8/41 , G06F17/16 , G06F7/5443 , G06F7/57 , G06F9/3001 , G06F9/30036 , G06F9/30192 , G06F9/3836 , G06F9/541 , G06F9/544 , G06F9/547 , H03M7/702
摘要： Apparatuses, systems, and techniques to perform an operation to indicate one or more non-zero values within one or more matrices of data; to perform an API to compress one or more matrices of data; to perform a matrix multiply accumulate (MMA) operation on two or more matrices of data, wherein at least one of the two or more matrices contain compressed data; and/or to perform an API to decompress one or more matrices of data. In at least one embodiment, one or more circuits are configured to receive and compile one or more instructions to perform computational operations for a sparse matrix multiplication.

8. 发明申请

WO2022212222A2 LIGHTWEIGHT ENCRYPTION 审中-公开
公开(公告)号：WO2022212222A2
公开(公告)日：2022-10-06
申请号：PCT/US2022/022076
申请日：2022-03-27
申请人： CYBERUS LABS SP. Z O.O. , WOLOSEWICZ, Jack
发明人： WOLOSEWICZ, Jack
IPC分类号： G06F21/60 , G06F9/32 , G06F9/54 , G06F21/78 , G06F21/602 , G06F9/321 , G06F9/544
摘要： Briefly, an encryption/decryption algorithm providing for consistent encryption entropy and encryption/decryption performance that is independent of the type of input data. The methods disclosed utilize two randomized lookup buffers, a key buffer and an offset buffer, as well as a histogram buffer. The two lookup buffers are initialized with a secret key shared (identical seed value) between the Client/Server (Or Hub/Device in the loT world).

9. 发明申请

WO2022211926A1 WAVE THROTTLING BASED ON A PARAMETER BUFFER 审中-公开
公开(公告)号：WO2022211926A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/017156
申请日：2022-02-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BRENNAN, Christopher J. , PATHAK, Nishank
IPC分类号： G06T1/60 , G06T1/20 , G06T15/80 , G06F9/542 , G06F9/544
摘要： A graphics pipeline (300) includes a first shader (305) that generates first wave groups, a shader processor input (SPI) (310) that launches the first wave groups for execution, and a scan converter (360) that generates second waves for execution based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache (340) holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.

10. 发明申请

WO2021201816A1 INFERENCE ENGINE CIRCUIT ARCHITECTURE 审中-公开
公开(公告)号：WO2021201816A1
公开(公告)日：2021-10-07
申请号：PCT/US2020/025592
申请日：2020-03-29
申请人： MICRON TECHNOLOGY, INC.
发明人： ZAIDY, Aliasger , CHANG, Andre Xian, Ming , CULURCIELLO, Eugenio
IPC分类号： G06F17/16 , G06N3/04 , G06N3/063 , G06F2207/4824 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/5027 , G06F9/544 , G06N3/0454
摘要： An inference engine circuit architecture is disclosed which includes a matrix-matrix (MM) processor circuit and a MM accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative MM accelerator circuit includes a first buffer circuit storing maps data; a first data network; multiple second buffer circuits each storing different kernel data; multiple second, serial data networks, with each coupled to a corresponding second buffer circuit; and a plurality of vector-vector (VV) acceleration circuits arranged in a plurality of arrays. Each VV acceleration circuit includes multiply and accumulate circuits; a shift register; a control multiplexer to provide a selected output, in response to a mode control word, of a bias parameter or a first accumulation sum; and a second adder circuit which adds the multiplicative product to the bias parameter or to the first accumulation sum to generate a second or next accumulation sum.

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