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    • 8. 发明公开
    • Radar apparatus
    • 雷达装置
    • EP1548460A1
    • 2005-06-29
    • EP04030287.9
    • 2004-12-21
    • TDK Corporation
    • Honya, TomohiroTomita, KatsuhikoIkeda, Hiroshi
    • G01S13/16G01R29/02G01R23/15
    • G01R29/023G01S13/103G01S13/16G01S13/931G01S17/105
    • A radar apparatus (1) includes a modulation signal generating unit (2) that generates a modulation signal (S TB ) based on an internal clock (CLK) with a cycle Tc and generates a trigger signal (S TG ) in synchronization with the modulation signal (S TB ), a carrier wave generating unit (3) that generates a carrier wave (S C ), a modulation unit (5) that generates and outputs a high frequency signal (S TR ) by modulating the carrier wave (S C ) using the modulation signal (S TB ), a modulation signal extracting unit (12) that extracts the modulation signal (S RB ) from a component of the high frequency signal (S RR ) that has been transmitted via a transmission antenna (6), the component having been reflected by a measured object (OB) and received by a reception antenna (11), a detection signal generating unit (15) that generates a detection signal (S d ), for measuring a distance to the measured object (OB), based on the trigger signal (S TG ) and the extracted modulation signal (S RB ), and a pulse width calculating unit (16) that calculates a pulse width (Tw) of the detection signal (S d ). The pulse width calculating unit (16) includes a delay circuit (DL1) that generates (n-1) delayed detection signals (S d2 ,...,S dn ) by delaying the inputted detection signal (S d ) by Tc/n, 2×Tc/n, ..., (n-1)×Tc/n, where n is a natural number of 2 or greater, n counter circuits (CNT11,...,CNT1n) that respectively carry out count operations in synchronization with rising or falling edges of the internal clock (CLK) while the detection signal (S d ) and the respective delayed detection signals (S d2 ,...,S dn ) are being inputted, and a calculating circuit (16) that calculates a sum of count values of the counter circuits (CNT11,...,CNT1n) and multiplies the sum by Tc/n to calculate the pulse width (Tw) of the detection signal (S d ).
    • 雷达装置(1)包括调制信号生成单元(2),该调制信号生成单元(2)基于具有周期Tc的内部时钟(CLK)生成调制信号(STB)并且生成与调制信号(STG)同步的触发信号 STB),生成载波(SC)的载波生成单元(3),通过使用调制信号(SC)对载波(SC)进行调制来生成并输出高频信号(STR)的调制单元(5) STB);调制信号提取单元(12),其从经由发送天线(6)发送的高频信号(SRR)的分量中提取调制信号(SRB),所述分量已经被测量 通过接收天线(11)接收对象(OB),检测信号生成部(15),基于该触发信号(STG),生成用于测定与被测定物(OB)的距离的检测信号(Sd) )和提取的调制信号(SRB)以及脉冲宽度ca 计算检测信号(Sd)的脉冲宽度(Tw)的计算单元(16)。 脉冲宽度计算单元(16)包括延迟电路(DL1),其通过将输入的检测信号(Sd)延迟Tc / n产生(n-1)个延迟的检测信号(Sd2,...,Sdn) Tc / n,...,(n-1)×Tc / n,其中n是2或更大的自然数,n个计数器电路(CNT11,...,CNT1n)分别执行与 在输入检测信号(Sd)和各个延迟检测信号(Sd2,...,Sdn)的同时,内部时钟(CLK)的上升沿或下降沿和计算电路(16) 计数器电路(CNT11,...,CNT1n)的值并且将和乘以Tc / n以计算检测信号(Sd)的脉冲宽度(Tw)。