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1. 发明公开

EP4440276A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：EP4440276A1
公开(公告)日：2024-10-02
申请号：EP23214205.9
申请日：2023-12-05
申请人： Samsung Electronics Co., Ltd.
发明人： JUNG, Myunghun , WOO, Kyuwon , SHIN, Donghwa , YEO, Sung-Jin , RYU, Ho-In
IPC分类号： H10B12/00
CPC分类号： H10B12/50 , H10B12/482 , H10B12/485 , H10B12/09
摘要： A semiconductor device includes a substrate including a cell block region and a peripheral region adjacent to each other in a first direction, first and second active patterns adjacent to each other in a second direction that is different from the first direction on the cell block region, a first bit line extending in the first direction on the first active pattern, a second bit line extending in the first direction on the second active pattern, a bit line connector connecting the first bit line and the second bit line to each other and adjacent to the peripheral region, an inner spacer on an inner surface of the bit line connector, and an outer spacer on an outer surface of the bit line connector. The inner spacer extends on (e.g., covers) the inner surface of the bit line connector and extends onto (e.g., continuously extends onto) inner surfaces of the first bit line and the second bit line.

3. 发明公开

EP4380331A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-实审
公开(公告)号：EP4380331A1
公开(公告)日：2024-06-05
申请号：EP23189041.9
申请日：2023-08-01
申请人： Samsung Electronics Co., Ltd.
发明人： JUNG, Myunghun , SHIN, Donghwa , YEO, Sung-Jin , RYU, Ho-In
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/50 , H10B12/09 , H10B12/315
摘要： A semiconductor device may include a substrate including a core region, a cell block region, and a peripheral region, which are sequentially arranged in a first direction, and a bit line structure on the cell block region. The bit line structure may include a first bit line and a second bit line, which extend in the first direction and are adjacent to each other in a second direction crossing the first direction, a bit line connector, which electrically connects the first bit line to the second bit line and is adjacent to the peripheral region, and a bit line pad, which is electrically connected to the first bit line and is adjacent to the core region.

4. 发明公开

EP4436329A1 INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：EP4436329A1
公开(公告)日：2024-09-25
申请号：EP24150208.7
申请日：2024-01-03
申请人： Samsung Electronics Co., Ltd.
发明人： PARK, Chanhoon , KIM, Jongkyu , KIM, Seunghoon , PARK, Sohyun , LEE, Woohyun
IPC分类号： H10B12/00
CPC分类号： H10B12/09 , H10B12/482 , H10B12/0335 , H10B12/053 , H10B12/315
摘要： An integrated circuit device includes a substrate having an active area, a plurality of bit line structures on the substrate, the plurality of bit line structures including insulating spacers on sidewalls thereof, a buried contact between the plurality of bit line structures and electrically connected to the active area, an insulation capping pattern on a bit line structure of the plurality of bit line structures, and a landing pad electrically connected to the buried contact, the landing pad arranged to vertically overlap the bit line structure on the insulation capping pattern, wherein an uppermost surface of the landing pad is higher than an uppermost surface of the insulation capping pattern, relative to the substrate.

5. 发明公开

EP4404711A1 SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4404711A1
公开(公告)日：2024-07-24
申请号：EP23218813.6
申请日：2023-12-20
申请人： Samsung Electronics Co., Ltd.
发明人： RIM, Taiuk , LEE, Jinseong , CHAE, Kyosuk
IPC分类号： H10B12/00
CPC分类号： H10B12/053 , H10B12/09 , H10B12/315 , H10B12/50
摘要： A semiconductor device may include a substrate including a cell region and a peripheral circuit region, a first gate structure in the cell region of the substrate, the first gate structure extending in a first direction parallel to an upper surface of the substrate, bit line structures on the cell region of the substrate, the bit line structures extending in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate, a second gate structure on the peripheral circuit region of the substrate, contact plug structures between the bit line structures, the contact plug structures contacting the substrate, first conductive structures on peripheral circuit region of the substrate, the first conductive structures being electrically connected to the peripheral circuit region of the substrate, a first upper insulation structure between the first conductive structures, the first upper insulation structure including a first upper insulation pattern and a hydrogen diffusing insulation pattern surrounding a bottom and sidewalls of the first upper insulation pattern, and a second upper insulation pattern between upper portions of the contact plug structures.

6. 发明公开

EP4376568A1 SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR, BIT LINE AND PERIPHERAL GATE 审中-实审
公开(公告)号：EP4376568A1
公开(公告)日：2024-05-29
申请号：EP23211234.2
申请日：2023-11-21
申请人： Samsung Electronics Co., Ltd.
发明人： SHIN, Joongchan , LEE, Kiseok , PARK, Seokhan , SHIN, Seokho
IPC分类号： H10B53/40 , H10B53/50 , H10B12/00 , H01L21/18
CPC分类号： H10B12/0335 , H10B12/033 , H10B12/09 , H10B12/482 , H10B12/50 , H10B12/315 , H01L21/185 , H10B53/50 , H10B53/40
摘要： A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.

7. 发明公开

US20240381625A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240381625A1
公开(公告)日：2024-11-14
申请号：US18505131
申请日：2023-11-09
申请人： SK hynix Inc.
发明人： Heon Yong CHANG
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/09 , H10B12/50
摘要： In a method of manufacturing a semiconductor device a substrate having a cell region and a peripheral region is prepared. A first cell-periphery structure including a conductive layer is formed over a surface of the substrate. In the cell region, a cell bit line trench is formed by patterning the first cell-periphery structure. A second cell-periphery structure including a second conductive layer is formed over the surface of the substrate. The second cell-periphery structure forms a cell bit line structure filling the cell bit line trench in the cell region, and is disposed over the first cell-periphery structure in the peripheral region. A periphery gate structure is formed by patterning the first and second cell-periphery structures in the peripheral region.

8. 发明公开

US20240334682A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20240334682A1
公开(公告)日：2024-10-03
申请号：US18522932
申请日：2023-11-29
申请人： Samsung Electronics Co., Ltd.
发明人： Bo Won YOO , Seok Han PARK , Ki Seok LEE , Hyun Geun CHOI , Jin Woo HAN
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/09 , H10B12/33 , H10B12/50
摘要： A semiconductor memory device with improved integration and electrical characteristics. The semiconductor memory device includes a peri-gate structure, a first peri-connecting structure on the peri-gate structure, a data storage pattern on the first peri-connecting structure, an active pattern that includes a first surface and a second surface opposite to each other in a first direction, and a first side wall and a second side wall opposite to each other in a second direction, the first surface of the active pattern connected to the data storage pattern and facing a substrate, a bit line on the active pattern, connected to the second surface of the active pattern, and extends in the second direction, a word line on the first side wall of the active pattern and extending in a third direction, a second peri-connecting structure connected to the bit line and a connecting pad connected to the second peri-connecting wiring.

9. 发明公开

US20240324172A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20240324172A1
公开(公告)日：2024-09-26
申请号：US18612672
申请日：2024-03-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Donghoon KWON , Yanghee Lee
IPC分类号： H10B12/00
CPC分类号： H10B12/09 , H10B12/0335
摘要： A method of manufacturing a semiconductor device includes preparing a substrate including a plurality of active regions and a peripheral active region defined by an isolation layer, forming a word line in a word line trench that crosses the plurality of active regions, forming a plurality of bit line structures, each of the plurality of bit line structures including a bit line on the plurality of active regions, forming a plurality of gate line structures, each of the plurality of gate line structures including a gate line on the peripheral active region, forming a plurality of buried contacts between the plurality of bit line structures, the plurality of buried contacts being connected to the plurality of active regions, and forming an inter-gate insulating layer between the plurality of gate line structures, the inter-gate insulating layer including an oxide having impurities.

10. 发明授权

US12100440B2 Sense amplifier circuit, method for operating same, and fabrication method for same 有权
公开(公告)号：US12100440B2
公开(公告)日：2024-09-24
申请号：US17828273
申请日：2022-05-31
申请人： Changxin Memory Technologies, Inc.
发明人： Qinghua Han
IPC分类号： G11C11/40 , G11C11/4091 , H10B12/00
CPC分类号： G11C11/4091 , H10B12/09
摘要： The invention provides a sense amplifier circuit, a method for operating same, and a fabrication method for same. The sense amplifier circuit includes: an amplifier electrically connected to a memory cell of a semiconductor memory; and a pre-amplifier located between the amplifier and the memory cell, where the pre-amplifier is configured to pre-amplify an electrical signal transmitted from the memory cell to the amplifier. In this way, the pre-amplifier is provided between the amplifier and the memory cell, such that the electrical signal stored in the semiconductor memory can be output after two stages of amplification by the pre-amplifier and the amplifier, thereby avoiding the problem that the electrical signal output from the memory cell cannot be accurately received and output in a case of a small sense margin of a signal of the sense amplifier.

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