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    • 5. 发明申请
    • COMMUNICATION ADAPTER
    • 通讯适配器
    • WO1990007849A1
    • 1990-07-12
    • PCT/EP1988001213
    • 1988-12-24
    • ALCATEL N.V.BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE ...
    • ALCATEL N.V.BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE ...BUSSCHAERT, Hans, Johan, JozefRABAEY, Dirk, Herman, Lutgardis, CorneliusREUSENS, Peter, Paul, Frans
    • H04Q11/04
    • H04Q11/0428H04L12/525
    • A multi-standard communication adapter (MSRA) for interfacing a low speed communication device (TP), e.g. a user station, and a high speed communication device (NP), e.g. an Integrated Services Digital Network (ISDN). Both these communication devices are allowed to transmit signals having electrical and functional interface characteristics which may be chosen amongst a wide variety of possible electrical and functional interface characteristics. The communication adapter is integrated in an electronic chip and is able to perform the different rate adaptation schemes owing to its programmable constituent parts (TXFR, TXUS, RXUS, RXFR, BUSA, BAUDA). The programmation of the communication adapter is realized by means of a host microprocessor external (PP) to the chip and which may also be used to temporarily store data transmitted between the two communication devices as well as to transmit information to or receive information from these devices. The communication adapter further includes a Baudrate generator (BAUDA) to control the clock signal on the low speed side (TP) and means to perform a self-test.
    • 用于连接低速通信设备(TP)的多标准通信适配器(MSRA),例如, 用户站和高速通信设备(NP),例如, 综合业务数字网(ISDN)。 这两个通信设备都允许发送具有电和功能接口特性的信号,这些信号可以在各种各样的可能的电和功能接口特性中选择。 通信适配器集成在电子芯片中,由于其可编程组成部分(TXFR,TXUS,RXUS,RXFR,BUSA,BAUDA)能够执行不同的速率适配方案。 通信适配器的编程通过对芯片的主机微处理器外部(PP)实现,并且还可以用于临时存储在两个通信设备之间传输的数据,以及向这些设备发送信息或从这些设备接收信息 。 通信适配器还包括用于控制低速侧(TP)上的时钟信号的波特率发生器(BAUDA)和进行自检的装置。
    • 8. 发明申请
    • CABLE SYSTEM FOR DIGITAL INFORMATION
    • 数字信号电缆系统
    • WO1987003439A1
    • 1987-06-04
    • PCT/US1986002565
    • 1986-11-26
    • TELENEX CORPORATION
    • TELENEX CORPORATIONROGERS, William, Paul
    • H04B03/00
    • H01R29/00H04L12/525H04L25/45
    • A cable system connects a plurality of parallel signals on a first set of plug contacts of a first plug at a modem, to a second set of plug contacts of a second plug at a CPU, or a remote terminal without requiring use of a large multiwire cable containing a wire for each signal. The cable system comprises a transmission line and two connector plug assemblies (66), one of the plug assemblies (66) being adapted to mate with the plug contacts of the plug at the modem and the other to mate with the plug contacts at the CPU or remote terminal. Each plug assembly contains a parallel-to-serial converter (96) and a serial-to-parallel converter (130); each parallel-to-serial converter (96) samples the parallel signals at its associated plug to produce time-multiplexed serial signals representing the parallel signals, and each serial-to-parallel converter (130) converts its received serial signal back to parallel.
    • 电缆系统将调制解调器上的第一插头的第一组插头触点上的多个并行信号连接到CPU或远程终端处的第二插头的第二组插头触点,而不需要使用大的多线 电缆包含每根信号的导线。 电缆系统包括传输线和两个连接器插头组件(66),其中一个插头组件(66)适于与调制解调器上的插头的插头触点相配合,而与CPU上的插头触点配合 或远程终端。 每个插头组件包含并行 - 串行转换器(96)和串行 - 并行转换器(130); 每个并行到串行转换器(96)在其相关联的插头处对并行信号进行采样以产生表示并行信号的时间多路复用的串行信号,并且每个串行到并行转换器(130)将其接收到的串行信号转换回并行。
    • 9. 再颁专利
    • Multiplex interface for a communication controller
    • 通讯控制器的多路复用接口
    • USRE34896E
    • 1995-04-04
    • US52189
    • 1991-05-29
    • Jean L. J. CalvignacJacques M. C. FeraudJean-Marie L. Munier
    • Jean L. J. CalvignacJacques M. C. FeraudJean-Marie L. Munier
    • G06F13/40H04L12/52H04J3/16H04J3/22
    • H04L12/525G06F13/4022
    • A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links. Both data and control bits are exchanged in synchronous frames wherein at least two slots are assigned to each user line, the structure of the two slots is identical for all types of user lines and includes an n-bit data slot having a variable number x of valid bits depending upon the line speed of the user line assigned to the data slot and indicated by a variable delimiter pattern comprising a first delimiting bit set at a first binary value (1) adjacent to the data bits and (n--x--1) bits set at the second binary value (0) adjacent to said first delimiting bit, and an n-bit control slot having a first bit used as a global validation bit in case the data slot comprises n valid bits (x.dbd.n), this bit being set at the first binary value (1) when the data slot comprises n valid bits and at the second binary value (0) if it comprises less than n valid bits, and the n--following bits are used for exchanging control information.
    • 一种多路复用接口,用于经由发送和接收同步多路复用链路将通信控制器的线路扫描装置(1)与用户线互连。 在同步帧中交换数据和控制位,其中至少两个时隙被分配给每个用户线,两个时隙的结构对于所有类型的用户线是相同的,并且包括具有可变数目x的n位数据时隙 有效位取决于分配给数据时隙的用户行的线速度,并且由可变分隔符模式指示,该可变分隔符模式包括在与数据位相邻的第一二进制值(1)和(nx-1)位设置下设置的第一定界位 在与所述第一定界位相邻的第二二进制值(0)处,以及在数据时隙包括n个有效位(x = n)的情况下具有用作全局验证位的第一位的n位控制时隙,该位为 如果数据时隙包括n个有效位,并且如果其包括小于n个有效位,则设置在第二二进制值(1)处,并且在第二个二进制值(0)处,并且将n个后续位用于交换控制信息。