专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1223678A3 Interleave circuit, de-interleave circuit and xDSL modem 审中-公开
标题翻译：交织，解交织和xDSL调制解调器
公开(公告)号：EP1223678A3
公开(公告)日：2003-10-22
申请号：EP01130717.0
申请日：2001-12-21
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Uto, Hiroshi
IPC分类号： H03M13/27
CPC分类号： H04L1/0041 , H03M13/2732 , H03M13/2764 , H03M13/2903 , H03M13/2957 , H03M13/6356 , H03M13/6533 , H04L1/0071 , H04L29/06 , H04L69/324
摘要： When a frame length N of input data is an even number, a read address generator generates twice in succession an address at which head byte data of each frame of the input data is stored. The head byte data of each frame of the input data is thus read from a memory twice in succession. The data of the frame length (N + 1) having the head byte data of each frame inserted as a dummy byte is then written to another memory according to a write address from a write address generator.

2. 发明公开

EP1476978A2 ASYMMETRIC DIGITAL SUBSCRIBER LINE MODEM APPARATUS AND METHODS THEREFOR 审中-公开
标题翻译：非对称数字用户线调制解调器装置及其方法
公开(公告)号：EP1476978A2
公开(公告)日：2004-11-17
申请号：EP03713281.8
申请日：2003-01-24
申请人： Broadcom Corporation
发明人： EFLAND, Gregory, H. , LIANG, Haixiang , PETERSON, kevin, H. , CHEN, Yuanjie , CORRY, Alan, G. , FERRARIO, Nino, P. , GUAN, Jeff, Z. , PRAHLAD, Meera , STOMAKHIN, Ilya , WAN, Yongbing , YAMANO, Larry, C. , YIN, Lin , YU, Gong-San , PAPANICOLAOU, George, A.
IPC分类号： H04L5/16
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem (100) including one or more processing paths. Also included is a number of interconnected modules (102) (104) (106) (108) sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

3. 发明授权

US08149904B2 Asymmetric digital subscriber line modem apparatus and methods therefor 失效
标题翻译：非对称数字用户线调制解调器及其方法
公开(公告)号：US08149904B2
公开(公告)日：2012-04-03
申请号：US10350279
申请日：2003-01-24
申请人： Gregory H. Efland , Haixiang Liang , Kevin H. Peterson , Yuanjie Chen , Alan G. Corry , Nino P. Ferrario , Jeff Z. Guan , Meera Prahlad , Ilya Stomakhin , Yongbing Wan , Larry C. Yamano , Lin Yin , Gong-San Yu , George A. Papanicolaou
发明人： Gregory H. Efland , Haixiang Liang , Kevin H. Peterson , Yuanjie Chen , Alan G. Corry , Nino P. Ferrario , Jeff Z. Guan , Meera Prahlad , Ilya Stomakhin , Yongbing Wan , Larry C. Yamano , Lin Yin , Gong-San Yu , George A. Papanicolaou
IPC分类号： H04B1/38
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

4. 发明授权

US07184468B2 Method and system for implementing a conditional one's complement of partial address 有权
标题翻译：实现部分地址条件补码的方法和系统
公开(公告)号：US07184468B2
公开(公告)日：2007-02-27
申请号：US10350294
申请日：2003-01-24
申请人： Gregory H. Efland
发明人： Gregory H. Efland
IPC分类号： H04B1/38
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

5. 发明申请

US20030097621A1 Efficient address generation for interleaver and de-interleaver 有权
标题翻译：交织器和解交织器的高效地址生成
公开(公告)号：US20030097621A1
公开(公告)日：2003-05-22
申请号：US10012834
申请日：2001-11-12
发明人： Weizhuang Xin
IPC分类号： G06F011/00
CPC分类号： H04L1/0071 , H03M13/2732 , H03M13/276 , H03M13/2782 , H03M13/6533 , H04L1/0043 , H04L1/0052
摘要： Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving. The present invention also provides for reading, writing, and updating offset registers in a code word by code word base manner.
摘要翻译：交织器和解交织器的高效地址生成。本发明通过采用能够跨越各种应用和平台适用的高效地址生成方案，在通信信道的相对端执行交织和解交织。本发明特别适用于呈现突发型噪声的通信信道。通过在通信信道的相对端采用交织和解交织，本发明能够提供一定程度的防止在通信信道内引起的数据损坏。本发明允许通过代码字对码字进行卷积交织和解交织操作。本发明提供了用于基于RAM的卷积交织和去交织的非常有效的地址生成。本发明还提供了通过代码字基本方式读取，写入和更新代码字中的偏移寄存器。

6. 发明申请

US20090135937A1 Trellis constellation shaping 审中-公开
标题翻译：网格星座塑形
公开(公告)号：US20090135937A1
公开(公告)日：2009-05-28
申请号：US12321912
申请日：2009-01-26
申请人： Igor S. Djokovic , Richard D. Wesel
发明人： Igor S. Djokovic , Richard D. Wesel
IPC分类号： H04L23/02
CPC分类号： H04L27/3411 , H03M13/253 , H03M13/256 , H03M13/2936 , H03M13/41 , H03M13/6533
摘要： A method for trellis constellation shaping is disclosed. In one embodiment, this method comprises receiving two or more input bits and filtering at least one of the two or more input bits to create two or more filtered output bits. The step of filtering at least one input bit introduces at least one extra bit. The method then encodes the input bits which are not filtered to create encoded bits and stores the encoded bits and the filtered bits in a buffer. A processing element may be configured to perform Viterbi type processing on the filtered bits to create processed bits. The method combines at least one of the processed bits with at least one of the buffered bits to create a combined bit set from the buffered bits and then performs mapping on the combined bet set to thereby map the combined bit set into a constellation.
摘要翻译：公开了一种网格星座成形方法。在一个实施例中，该方法包括接收两个或更多个输入比特并且对两个或更多个输入比特中的至少一个进行滤波以创建两个或多个滤波输出比特。对至少一个输入位进行滤波的步骤至少引入一个额外的位。然后，该方法对未被滤波的输入位进行编码以创建编码比特，并将编码比特和滤波比特存储在缓冲器中。处理元件可以被配置为对滤波的比特执行维特比类型处理以创建经处理的比特。该方法将经处理的比特中的至少一个与缓冲比特中的至少一个相结合，以从缓冲的比特中产生组合的比特集合，然后在组合的赌注集上执行映射，从而将组合比特集合映射成星座。

7. 发明授权

US07177988B2 Method and system for synchronizing processor and DMA using ownership flags 失效
标题翻译：使用所有权标志同步处理器和DMA的方法和系统
公开(公告)号：US07177988B2
公开(公告)日：2007-02-13
申请号：US10350287
申请日：2003-01-24
申请人： Gregory H. Efland , Jeff Z. Guan , Gong-San Yu
发明人： Gregory H. Efland , Jeff Z. Guan , Gong-San Yu
IPC分类号： G06F13/18
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

8. 发明申请

US20030225958A1 Method and system for copying DMA with separate strides by a modulo-n counter 失效
标题翻译：通过模数n计数器复制具有单独步幅的DMA的方法和系统
公开(公告)号：US20030225958A1
公开(公告)日：2003-12-04
申请号：US10350296
申请日：2003-01-24
发明人： Gregory H. Efland , Jeff Z. Guan , Lin Yin
IPC分类号： G11C005/00
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

9. 发明申请

WO2003063060A2 ASYMMETRIC DIGITAL SUBSCRIBER LINE MODEM APPARATUS AND METHODS THEREFOR 审中-公开
标题翻译：不对称数字订户线路调制解调器及其方法
公开(公告)号：WO2003063060A2
公开(公告)日：2003-07-31
申请号：PCT/US2003/002154
申请日：2003-01-24
申请人： BROADCOM CORPORATION
发明人： EFLAND, Gregory, H. , LIANG, Haixiang , PETERSON, kevin, H. , CHEN, Yuanjie , CORRY, Alan, G. , FERRARIO, Nino, P. , GUAN, Jeff, Z. , PRAHLAD, Meera , STOMAKHIN, Ilya , WAN, Yongbing , YAMANO, Larry, C. , YIN, Lin , YU, Gong-San , PAPANICOLAOU, George, A.
IPC分类号： G06K
CPC分类号： H04L7/0012 , G06F9/52 , H03M13/2732 , H03M13/6533 , H04L1/0071 , H04L7/0029 , H04L25/03159 , H04L27/2647 , H04L45/00 , H04L49/90 , H04L2012/5681 , H04M11/062
摘要： Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
摘要翻译：提供了一种用于包括一个或多个处理路径的调制解调器的系统和方法。还包括沿着一个或多个路径顺序排列的多个互连模块。每个模块被配置为（i）根据顺序处理沿着路径传递的信号，以及（ii）实现预定功能以执行处理。此外，每个模块具有特定程度的功能可编程性，并且功能可编程性的程度根据顺序单调变化。

10. 发明授权

US08555149B2 Systems and methods for protecting DSL systems against impulse noise 失效
标题翻译：保护DSL系统免受脉冲噪声的系统和方法
公开(公告)号：US08555149B2
公开(公告)日：2013-10-08
申请号：US12411511
申请日：2009-03-26
申请人： Julien D. Pons , Ravindra M Lambi , Patrick Duvaut , Massimo Sorbara
发明人： Julien D. Pons , Ravindra M Lambi , Patrick Duvaut , Massimo Sorbara
IPC分类号： G06F11/00
CPC分类号： H04L1/1835 , H03M13/1515 , H03M13/6306 , H03M13/6533 , H04L1/0045 , H04L1/0057 , H04L1/0071 , H04L1/1838 , H04L1/1858
摘要： Systems and methods for protecting DSL systems against impulse noise are provided. Disclosed herein are example embodiments of a retransmission technique located above the gamma interface (i.e., in the network processing layer). Such a retransmission technique can be combined with standard RS coding with standard erasure-decoding & triangular interleaving at the PMS-TC layer. Example embodiments of the technique involve using the RS code to protect against REIN noise, and using γ-layer retransmission for protecting against error events not corrected by the RS code, e.g. a SHINE noise in the presence of REIN. Both techniques are used jointly in the case of combined REIN and SHINE noise.
摘要翻译：提供了用于保护DSL系统免受脉冲噪声的系统和方法。这里公开了位于伽马接口（即网络处理层）之上的重传技术的示例实施例。这样的重传技术可以与在PMS-TC层的标准擦除解码和三角形交织的标准RS编码组合。该技术的示例实施例涉及使用RS码来防止REIN噪声，并且使用伽玛层重传来防止未被RS码校正的错误事件，例如，在REIN存在下的SHINE噪音。两种技术在组合REIN和SHINE噪声的情况下共同使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式