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    • 7. 发明授权
    • Frequency modulation demodulation system
    • 频率调制解调系统
    • US3643172A
    • 1972-02-15
    • US3643172D
    • 1969-03-18
    • ITT
    • RABOW GERALD
    • H03D3/00H03D3/24
    • H03D3/248H03D3/002
    • An iterative-type FM demodulator comprises a first FMFB demodulator coupled to the original input signal. The output of the first demodulator is coupled to modulate a voltage-controlled oscillator. The oscillator output is mixed with the original input signal. The resultant output of the mixer is demodulated by a second FM demodulator which may be of the feedback type. The output of the second demodulator is added as a correction signal to the output of the first demodulator to provide the desired system output signal. This system has greater threshold extension than obtainable with presently employed FMFB demodulator. The circuit arrangement coupled to the output of the first demodulator may be repeated a number of times and coupled in cascade with each other to provide a further threshold extension.
    • 迭代型FM解调器包括耦合到原始输入信号的第一FMFB解调器。 第一解调器的输出被耦合以调制压控振荡器。 振荡器输出与原始输入信号混合。 混频器的结果输出由可能是反馈类型的第二FM解调器解调。 将第二解调器的输出作为校正信号添加到第一解调器的输出端以提供期望的系统输出信号。 该系统具有比目前使用的FMFB解调器可获得的阈值扩展更大的阈值。 耦合到第一解调器的输出的电路装置可以重复多次并且彼此级联耦合以提供另外的阈值扩展。
    • 9. 发明申请
    • MULTIPLE USE OF AN FM BAND
    • FM带的多次使用
    • WO1990002445A1
    • 1990-03-08
    • PCT/US1989003388
    • 1989-08-07
    • MYERS, Glen, A.
    • H03D03/00
    • H03D3/248
    • A signal receiving system (10) for receiving messages from each of several unequal amplitude FM carriers (vi(t)) occupying the same portion of the frequency band. The capture effect associated with conventional frequency demodulators is utilized in a series of successively coupled phase lock loops (PLL1, PLL2, PLL3, ..., PLLN) to provide demodulation of all of several FM carrier signals including weaker carrier signals in the presence of dominant carrier signals. A phase lock loop demodulator (PLL1) provides a demodulated signal representing the information contained in the most dominant carrier signal input to the phase lock loop (PLL1). The phase lock loop (PLL1) also provides a replica signal (Yi(t)) which is identified to the most dominant carrier signal input. The input signal (Vi(t)) is also delayed in a delay circuit (105) and input into an input port of an output circuit (106). The replica signal (Yi(t)) is also coupled to an input port of the output circuit (106). The output circuit (106) produces an output signal (Zi(t)) which is identical to the input signal (Vi(t)) except that the most dominant carrier signal is suppressed. The output signal (Zi(t)) is then coupled to a successive phase lock loop (PLL2) and delay (115).