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1. 发明公开

CN103069931A 导电性表面安装端子用膜及其制备方法无效
公开(公告)号：CN103069931A
公开(公告)日：2013-04-24
申请号：CN201080068521.0
申请日：2010-08-23
申请人：斗星产业株式会社
发明人：黄太助 , 李常源 , 林恩我 , 郑哲和
IPC分类号： H05K1/03 , H05K1/09 , H05K3/38 , H01L21/60 , H01B5/14
CPC分类号： H05K3/4015 , H01L23/49811 , H01L24/65 , H01L24/66 , H01L24/89 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01R12/57 , H01L2924/00
摘要：本发明提供一种导电性表面安装端子用膜。本发明的导电性表面安装端子用膜包括：耐热膜，以及金属层，与上述耐热膜的表面相接触形成；或者本发明的导电性表面安装端子用膜包括：第一金属层，耐热膜，其与形成在上述第一金属层的表面相接触而形成，以及第二金属层，其与形成在上述耐热膜的另一表面相接触而形成。本发明的导电性表面安装端子用膜在反流焊接工序中与被焊膏溶解的锡成分相互之间顺利相结合，而不产生端子的滑移现象，从而可以将导电性表面安装端子安装在原位置。据此，如果将适用本发明的导电性表面安装端子用膜的端子适用于基板，则不会对电流的流动或者微小信号产生坏影响，从而电子设备出现故障的忧虑少。

2. 发明授权

US09661756B1 Nano-copper pillar interconnects and methods thereof 有权
公开(公告)号：US09661756B1
公开(公告)日：2017-05-23
申请号：US14455642
申请日：2014-08-08
申请人： Flextronics AP, LLC
发明人： Jennifer Nguyen , David Geiger , Anwar Mohammed , Murad Kurwa
IPC分类号： H05K1/09 , H05K3/24 , H05K1/11 , H05K3/30 , H05K3/40
CPC分类号： H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要： Embodiments of the present invention relate to nano-copper pillar interconnects. Nano-copper material is a mixture of nano-copper particles and one or more organic fluxes. In some embodiments, the one or more organic fluxes include organic solvents that help bind the nano-copper particles together and allow the nano-copper material to be printable. The nano-copper material is applied onto bond pads on a printed circuit board (PCB) via a printing process, a dipping process or the like, to form nano-copper covered PCB bond pads. A component can thereafter be coupled with the PCB at the nano-copper covered PCB bond pads. What is left when the solvents evaporate are nano-copper pillar interconnects that form, coupling the component with the PCB bond pads. The nano-copper pillar interconnects are of pure copper.

3. 发明授权

US09397065B1 Fixture design for pre-attachment package on package component assembly 有权
标题翻译：夹具组件装配前套件的夹具设计
公开(公告)号：US09397065B1
公开(公告)日：2016-07-19
申请号：US14468216
申请日：2014-08-25
申请人： Flextronics AP, LLC
发明人： Jennifer Nguyen , David Geiger , Ranilo Aranda , Jonas Sjoberg , Anwar Mohammed , Murad Kurwa
IPC分类号： H01L23/544 , H01L23/00 , H01L25/00 , H01L23/538
CPC分类号： H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要： Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a plurality of pockets arranged in a N×M array. The plurality of pockets is sized to receive bottom packages. The fixture design includes global fiducials that are used to locate positions of the pockets on the fixture, and sets of local fiducials, with each set being specific to one of the pockets and used to refine the position of the location of a corresponding pocket. Each of the pockets can include one or more ear cuts for easy component placement and component removal. The fixture design can include a vacuum port for coupling with a vacuum source for drawing a vacuum to hold the bottom packages down. The fixture design can also include a cover that is used with the fixture to keep the components from being disturbed.
摘要翻译：本发明的实施例涉及一种用于包装部件组件上的预附接包装的夹具设计。夹具设计包括以N×M阵列排列的多个口袋。多个口袋的尺寸适于接纳底部包装。夹具设计包括用于定位夹具上的凹穴的位置的全局基准和局部基准的集合，其中每一组特定于其中一个凹穴并且用于细化相应凹穴的位置的位置。每个口袋可以包括一个或多个耳朵切口，便于元件放置和元件移除。夹具设计可以包括用于与真空源耦合的真空端口，用于抽真空以将底部包装件向下保持。夹具设计还可以包括与夹具一起使用以防止部件受到干扰的盖子。

4. 发明授权

US07592699B2 Hidden plating traces 有权
标题翻译：隐藏电镀痕迹
公开(公告)号：US07592699B2
公开(公告)日：2009-09-22
申请号：US11321929
申请日：2005-12-29
申请人： Hem Takiar , Cheemen Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheemen Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L23/04
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
摘要翻译：公开了一种加强的半导体管芯基板和封装。衬底可以包括形成有非线性边缘的接触指状物。向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

5. 发明申请

US20070152319A1 Hidden plating traces 有权
标题翻译：隐藏电镀痕迹
公开(公告)号：US20070152319A1
公开(公告)日：2007-07-05
申请号：US11321929
申请日：2005-12-29
申请人： Hem Takiar , Cheemen Yu , Ken Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheemen Yu , Ken Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
摘要翻译：公开了一种加强的半导体管芯基板和封装。衬底可以包括形成有非线性边缘的接触指状物。向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

6. 发明授权

US09209159B2 Hidden plating traces 有权
公开(公告)号：US09209159B2
公开(公告)日：2015-12-08
申请号：US13411308
申请日：2012-03-02
申请人： Hem Takiar , Cheeman Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheeman Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L23/04 , H01L25/065 , H01L23/538 , H01L23/00 , H01L21/3205 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

7. 发明申请

US20120164828A1 HIDDEN PLATING TRACES 有权
标题翻译：隐藏的镀层
公开(公告)号：US20120164828A1
公开(公告)日：2012-06-28
申请号：US13411308
申请日：2012-03-02
申请人： Hem Takiar , Cheeman Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheeman Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L21/3205
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
摘要翻译：公开了一种加强的半导体管芯基板和封装。衬底可以包括形成有非线性边缘的接触指状物。向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

8. 发明授权

US09053405B1 Printed RFID circuit 有权
标题翻译：打印RFID电路
公开(公告)号：US09053405B1
公开(公告)日：2015-06-09
申请号：US14162483
申请日：2014-01-23
申请人： Flextronics AP, LLC
发明人： Weifeng Liu , Anwar Mohammed , Murad Kurwa
IPC分类号： G06K19/07 , G06K19/077 , H01M6/40
CPC分类号： H05K3/244 , G06K19/07754 , H01L23/5386 , H01L24/65 , H01L25/00 , H01L2924/38 , H01M6/40 , H04B1/3816 , H05K1/097 , H05K1/111 , H05K3/30 , H05K3/40
摘要： A printed circuit including a non-conductive substrate, a first conductive layer printed on the non-conductive substrate and one or more additional layers printed on the substrate. The first conductive layer is able to have one or more antennas each forming a predetermined pattern, a first conductive sheet and one or more conductive traces. The one or more additional layers include a first electrode printed on the top of the first conductive sheet, a buffer printed on top of the first electrode, a second electrode printed on top of the buffer and a second conductive sheet printed on top of the second electrode. The printed circuit is further able to include an RFID chip electrically coupled with the antennas and at least one of the first and second conductive sheets via the conductive traces, wherein the first and second conductive sheets, the buffer and the first and second electrodes form a power source that provides electrical power to the RFID chip.
摘要翻译：一种印刷电路，包括非导电衬底，印刷在非导电衬底上的第一导电层和印刷在衬底上的一个或多个附加层。第一导电层能够具有各自形成预定图案的一个或多个天线，第一导电片和一个或多个导电迹线。所述一个或多个附加层包括印刷在第一导电片的顶部上的第一电极，印刷在第一电极顶部上的缓冲器，印刷在缓冲器顶部的第二电极和印刷在第二导电片的第二个顶部上的第二导电片电极。印刷电路还能够包括通过导电迹线与天线以及第一和第二导电片中的至少一个电耦合的RFID芯片，其中第一和第二导电片，缓冲器和第一和第二电极形成向RFID芯片提供电力的电源。

9. 发明授权

US08129272B2 Hidden plating traces 有权
标题翻译：隐藏电镀痕迹
公开(公告)号：US08129272B2
公开(公告)日：2012-03-06
申请号：US12493582
申请日：2009-06-29
申请人： Hem Takiar , Cheeman Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheeman Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L21/44
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
摘要翻译：公开了一种加强的半导体管芯基板和封装。衬底可以包括形成有非线性边缘的接触指状物。向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

10. 发明申请

US20090263969A1 HIDDEN PLATING TRACES 有权
标题翻译：隐藏的镀层
公开(公告)号：US20090263969A1
公开(公告)日：2009-10-22
申请号：US12493582
申请日：2009-06-29
申请人： Hem Takiar , Cheemen Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
发明人： Hem Takiar , Cheemen Yu , Ken Jian Ming Wang , Chin-Tien Chiu , Han-Shiao Chen , Chih-Chin Liao
IPC分类号： H01L21/3205
CPC分类号： H01L25/0657 , H01L21/3205 , H01L23/04 , H01L23/3121 , H01L23/5386 , H01L24/48 , H01L24/64 , H01L24/65 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
摘要翻译：公开了一种加强的半导体管芯基板和封装。衬底可以包括形成有非线性边缘的接触指状物。向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

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