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    • 8. 发明申请
    • PIEZOELECTRIC AND LOGIC INTEGRATED DELAY LINE MEMORY
    • 压电和逻辑集成延迟线存储器
    • WO2015138058A3
    • 2015-12-30
    • PCT/US2015014324
    • 2015-02-03
    • UNIV CORNELL
    • LAL AMITKUO JUSTIN C
    • G11C21/02
    • G11C21/023B06B1/0215B06B2201/20B06B2201/55B06B2201/70G11C7/16G11C19/00G11C2013/0095
    • Delay line memory device, systems and methods are disclosed. In one aspect, a delay line memory device includes a substrate; an electronic unit disposed on the substrate and operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device; a first and a second piezoelectric transducer disposed on the substrate and in communication with the electronic unit, in which the first piezoelectric transducer is operable to transmit the data signals to the acoustic pulses that carry the data through the bulk of the substrate, and the second piezoelectric transducer is operable to transduce the received acoustic pulses to intermediate electrical signals containing the data, which are transferred to the electronic unit via an electrical interconnect to cause refresh of the data in the delay line memory device.
    • 延迟线存储器装置,系统和方法被公开。 在一个方面,延迟线存储器装置包括衬底; 电子单元,其设置在所述基板上,并且可操作以将数据信号接收,放大和/或同步成比特流,以作为传送存储在所述延迟线存储器设备中的数据的声脉冲发送; 第一压电换能器和第二压电换能器,设置在所述基板上并与所述电子单元通信,其中所述第一压电换能器可操作以将所述数据信号传输到承载所述数据通过所述基板本体的所述声学脉冲,并且所述第二 压电换能器可操作地将所接收的声脉冲转换成包含数据的中间电信号,所述数据经由电互连被传送到电子单元以引起延迟线存储器装置中的数据的刷新。