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1. 发明公开

US20230281156A1 PARTITIONING DATAFLOW OPERATIONS FOR A RECONFIGURABLE COMPUTING SYSTEM 审中-公开
公开(公告)号：US20230281156A1
公开(公告)日：2023-09-07
申请号：US17894127
申请日：2022-08-23
申请人： SambaNova Systems, Inc.
发明人： Yaqi Zhang , Mark Wagner , Matthew Feldman , Weiwei Chen
IPC分类号： G06F15/78 , G06F9/50
CPC分类号： G06F15/7875 , G06F9/5044
摘要： A method for partitioning executable operations for a reconfigurable computing system includes receiving a set of expressions comprising a plurality of operations and dependencies for those operations, partitioning the plurality of operations into selected executable partitions wherein each selected executable partition conforms to resource constraints for a reconfigurable unit of the reconfigurable computing system. Partitioning the plurality of operations into selected executable partitions may include seeding a candidate partition with an operation, recursively generating an additional candidate partition for each operation adjacent to the candidate partition whose dependent operations are already within the candidate partition or a previously selected partition, and selecting a best candidate partition based on resource cost. A corresponding system and computer-readable medium are also disclosed herein. The system includes a partitioning module that that partitions the plurality of operations into selected executable partitions according to the method describe above.

2. 发明申请

US20190004994A1 PROCESSORS AND METHODS FOR PIPELINED RUNTIME SERVICES IN A SPATIAL ARRAY 审中-公开
公开(公告)号：US20190004994A1
公开(公告)日：2019-01-03
申请号：US15640538
申请日：2017-07-01
申请人： KERMIN FLEMING , SIMON C. STEELY , KENT D. GLOSSOP
发明人： KERMIN FLEMING , SIMON C. STEELY , KENT D. GLOSSOP
IPC分类号： G06F15/78 , G06F15/82 , G06F15/80
CPC分类号： G06F15/7878 , G06F15/7875 , G06F15/80 , G06F15/825
摘要： Methods and apparatuses relating to pipelined runtime services in spatial arrays are described. In one embodiment, a processor includes processing elements; an interconnect network between the processing elements; a first configuration controller coupled to a first subset of the processing elements; and a second configuration controller coupled to a second, different subset of the processing elements, the first configuration controller and the second configuration controller are to configure the first subset and the second, different subset according to configuration information for a first context, and, for a context switch, the first configuration controller is to configure the first subset according to configuration information for a second context after pending operations of the first context are completed in the first subset and block second context dataflow into the second, different subset's input from the first subset's output until pending operations of the first context are completed in the second, different subset.

3. 发明公开

EP4394616A1 PROGRAMMABLE HARDWARE ACCELERATOR CONTROLLER 审中-公开
公开(公告)号：EP4394616A1
公开(公告)日：2024-07-03
申请号：EP23216045.7
申请日：2023-12-12
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： ZAMBOTTI, Paolo Sergio , BOESCH, Thomas , DESOLI, Giuseppe , BETZ, Wolfgang Johann , SIORPAES, David
IPC分类号： G06F15/78
CPC分类号： G06F15/7875 , G06F15/7889
摘要： A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.

4. 发明授权

EP3710948B1 VIRTUAL FPGA MANAGEMENT AND OPTIMIZATION SYSTEM 有权
公开(公告)号：EP3710948B1
公开(公告)日：2024-05-01
申请号：EP18755952.1
申请日：2018-07-13
IPC分类号： G06F30/34 , G06F9/48 , G06F9/50 , G06F15/76 , G06F15/78 , H03K19/17728 , H03K19/17732 , H03K19/17756 , H03K19/1776
CPC分类号： G06F15/76 , G06F15/7871 , G06F15/7875 , G06F9/4843 , G06F9/5011 , G06F9/5077 , H03K19/17728 , H03K19/17732 , H03K19/1776 , H03K19/17756 , G06F30/34 , G06F30/30

5. 发明授权

US11656971B2 Technology for dynamically tuning processor features 有权
公开(公告)号：US11656971B2
公开(公告)日：2023-05-23
申请号：US17582051
申请日：2022-01-24
申请人： Intel Corporation
发明人： Adarsh Chauhan , Jayesh Gaur , Franck Sala , Lihu Rappoport , Zeev Sperber , Adi Yoaz , Sreenivas Subramoney
IPC分类号： G06F11/34 , G06F11/30 , G06F15/78 , G06F9/24 , G06F9/38
CPC分类号： G06F11/3476 , G06F9/24 , G06F9/3836 , G06F11/3024 , G06F11/3055 , G06F15/7875
摘要： A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

6. 发明申请

US20170185564A1 PROCESSOR, METHOD FOR CONTROLLING RECONFIGURABLE CIRCUIT AND PROGRAM 审中-公开
公开(公告)号：US20170185564A1
公开(公告)日：2017-06-29
申请号：US15290071
申请日：2016-10-11
申请人： FUJITSU LIMITED
发明人： Masahiko Toichi
IPC分类号： G06F15/78 , G06F9/48
CPC分类号： G06F15/7875 , G06F9/485 , G06F9/4881 , G06F15/7871
摘要： A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.

7. 发明授权

US09575776B2 System for organizing and guiding a user in the experience of browsing different applications based on contexts 有权
标题翻译：用于组织和指导用户基于上下文浏览不同应用程序的体验的系统
公开(公告)号：US09575776B2
公开(公告)日：2017-02-21
申请号：US12981643
申请日：2010-12-30
申请人： Tiago Silveira De Andrade Cajahyba , Alexandre Bader Krafzik , Eduardo Manuel De Freitas Jorge , Alberto Almeida De Azevedo Filho , Fernando Campos Martins , Ana Lúcia Lage Pereira , Talmai Brandão De Oliveira , Hernane Borges De Barros Pereira , Fabíola De Lima Moreira
发明人： Tiago Silveira De Andrade Cajahyba , Alexandre Bader Krafzik , Eduardo Manuel De Freitas Jorge , Alberto Almeida De Azevedo Filho , Fernando Campos Martins , Ana Lúcia Lage Pereira , Talmai Brandão De Oliveira , Hernane Borges De Barros Pereira , Fabíola De Lima Moreira
IPC分类号： G06F15/16 , G06F9/445 , G06F17/30 , G06F9/45 , H04L29/08 , G06F9/44 , G06F15/78
CPC分类号： G06F9/44505 , G06F8/43 , G06F9/451 , G06F15/7875 , G06F17/30528 , H04L29/08072
摘要： The present invention provides a system that enhances the experience of using a portable device such as mobile phones, smart phones, Personal Digital Assistants PDA etc. To improve the user experience in the use of a portable device, techniques are used for “context characterization, i.e., from a range of conditions possible to detect by the system, such as time (date/time), current location, motion, etc., as well as the historical use of the device, a certain grouping of actions and settings, called “context” are selected automatically or manually, modifying and setting from that moment the way of user interacts with the device.
摘要翻译：本发明提供了增强使用便携式设备（例如移动电话，智能电话，个人数字助理PDA等）的经验的系统。为了改善使用便携式设备的用户体验，使用了“上下文表征，即从系统可以检测的一系列条件，例如时间（日期/时间），当前位置，运动等，以及设备的历史使用，一组动作和设置，称为自动或手动选择“上下文”，从用户与设备进行交互的方式修改和设置。

8. 发明申请

US20130002292A1 RECONFIGURABLE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：可重构集成电路设备
公开(公告)号：US20130002292A1
公开(公告)日：2013-01-03
申请号：US13458255
申请日：2012-04-27
申请人： Hayato HIGUCHI , Takashi Hanai
发明人： Hayato HIGUCHI , Takashi Hanai
IPC分类号： G06F7/38
CPC分类号： G06F15/7875 , G06F15/7867
摘要： A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.
摘要翻译：可重构集成电路装置包括多个处理元件，每个处理元件包括运算电路，并且被配置为基于配置数据的任何计算状态; 以及基于配置数据在任何状态下连接处理元件的相互处理元件网络。并且处理元件输入输入有效信号和输入数据信号，并输出输出有效信号和输出数据信号，并且包括输入数据保持寄存器，运算处理电路和保持计算的输出数据保持寄存器结果数据，并且当通过使保持模式有效的配置数据来更新配置时，无论输入有效信号如何有效或无效，输入数据保持寄存器在更新时保持输入数据信号，并且运算处理电路执行计算对保存在输入数据保持寄存器中的输入数据信号进行处理。

9. 发明公开

US20240264975A1 Reconfigurable Parallel Processing 审中-公开
公开(公告)号：US20240264975A1
公开(公告)日：2024-08-08
申请号：US18619382
申请日：2024-03-28
申请人： XDL Technologies Inc.
发明人： Yuan Li , Jianbin Zhu
IPC分类号： G06F15/80 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/445 , G06F12/0815 , G06F13/16 , G06F15/78
CPC分类号： G06F15/8023 , G06F9/3001 , G06F9/3004 , G06F9/3009 , G06F9/30098 , G06F9/34 , G06F9/3808 , G06F9/3867 , G06F9/3885 , G06F9/44505 , G06F12/0815 , G06F13/1673 , G06F15/7821 , G06F15/7867 , G06F15/7871 , G06F15/7875 , G06F15/7878 , G06F15/7885 , G06F15/7889 , G06F15/8046 , G06F15/8061 , G06F15/8069 , G06F15/8092 , G06F2212/1021 , Y02D10/00
摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.

10. 发明申请

US20180357202A1 DYNAMIC CONFIGURATION OF HARDWARE 审中-公开
公开(公告)号：US20180357202A1
公开(公告)日：2018-12-13
申请号：US15616085
申请日：2017-06-07
申请人： ARM LIMITED
发明人： Sami Ur Rehman Zia Ur Rehman MUJAWAR
IPC分类号： G06F15/78 , G06F9/44
CPC分类号： G06F15/7882 , G06F9/4405 , G06F9/4406 , G06F15/7875
摘要： A data processing apparatus is provided. The data processing apparatus includes hardware locating circuitry for locating hardware associated with processing circuitry, and for causing hardware configuration data relating to the hardware to be generated. Providing circuitry causes the hardware configuration data to be provided to an operating system executing on the processing circuitry to enable the operating system to utilise the hardware.

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