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1. 发明专利

JP2004311891A Semiconductor device 审中-公开
公开(公告)号：JP2004311891A
公开(公告)日：2004-11-04
申请号：JP2003106582
申请日：2003-04-10
申请人： Seiko Instruments Inc , Silterra Malaysia Sdn Bhd , シルテラマレーシアエスディエヌ.ビーエッチディ , セイコーインスツルメンツ株式会社
发明人： INOUE SHIGETO , WATANABE HITOMI , PAEK MIN , KIM SANG-YONG , KIM INKI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/76
CPC分类号： H01L27/0921 , H01L21/76237 , H01L21/823814 , H01L21/823878
摘要： PROBLEM TO BE SOLVED: To prevent parasitic transistor operation, and simplify and refining a process, in a semiconductor device in which a high breakdown voltage MOS transistor and a low breakdown voltage one are present mixedly.
SOLUTION: When the high breakdown voltage MOS transistor and a fine low breakdown voltage MOS transistor are mixedly mounted on a same semiconductor substrate, two STIs (shallow trench isolations) are used, an active region, where high concentration impurities are doped in the channel region of a parasitic MOS transistor, is provided between the STIs and current flowing between the source and drain of the parasitic MOS transistor is interrupted.
COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

TWI464803B 在溝槽中製成底部氧化層之方法有权
简体标题：在沟槽中制成底部氧化层之方法
公开(公告)号：TWI464803B
公开(公告)日：2014-12-11
申请号：TW101118229
申请日：2012-05-22
申请人：席特拉馬來西亞有限公司 , SILTERRA MALAYSIA SDN BHD
发明人：鄭查理 , TAY, CHARLIE , 馬哈文汎卡帝西 , MADHAVEN, VENKATESH , 甘地馬哈地阿俊庫馬 , KANTIMAHANTI, ARJUN KUMAR
IPC分类号： H01L21/31
CPC分类号： H01L29/4236 , H01L21/31144 , H01L29/66621

3. 发明申请

WO2019066637A1 MONOLITHIC INTEGRATION OF PMUT ON CMOS 审中-公开
公开(公告)号：WO2019066637A1
公开(公告)日：2019-04-04
申请号：PCT/MY2018/050055
申请日：2018-08-21
申请人： SILTERRA MALAYSIA SDN. BHD.
发明人： SOUNDARA PANDIAN, Mohanraj , KANTIMAHANTI, Arjun Kumar
IPC分类号： H01L41/09 , H01L27/20 , B06B1/06 , B81B3/00
摘要： This disclosure describes a monolithic integrated device that comprises a substrate layer (101) being the base of the device; an inter-layer dielectric (102) disposed on top of the substrate layer (101) and below a passivation layer (103); an electronic circuitry formed within the inter-layer dielectric (102) and supported by the substrate layer (101), the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals (204); and at least one micromachined ultrasonic transducer. Each micromachined ultrasonic transducer comprises a bottom electrode (301) disposed on top of the passivation layer (103) and connected to the electronic circuitry; a piezoelectric (302) disposed on top of the bottom electrode (301); a top electrode (303) disposed on top of the piezoelectric; and an elastic layer (304) positioned on top of the top electrode (303). There is a cavity (306) formed below the bottom electrode (301) that extends from the passivation layer (103) to a portion of the inter-layer dielectric (102). (The Most Illustrative Drawing:

4. 发明专利

TWI689461B CMOS上的PMUT的單石積體有权
简体标题： CMOS上的PMUT的单石积体
公开(公告)号：TWI689461B
公开(公告)日：2020-04-01
申请号：TW107130662
申请日：2018-08-31
申请人：馬來西亞商矽特拉有限公司 , SILTERRA MALAYSIA SDN. BHD.
发明人：紹達拉潘迪安莫罕拉吉 , SOUNDARA PANDIAN, MOHANRAJ , 坎帝馬翰帝阿君庫馬爾 , KANTIMAHANTI, ARJUN KUMAR
IPC分类号： B81B7/00 , B06B1/06

5. 发明申请

WO2018101814A1 MONOLITHIC INTEGRATED DEVICE 审中-公开
公开(公告)号：WO2018101814A1
公开(公告)日：2018-06-07
申请号：PCT/MY2017/050071
申请日：2017-11-15
申请人： SILTERRA MALAYSIA SDN. BHD.
发明人： SOUNDARA PANDIAN, Mohanraj , TAY, Wee Song , MADHAVEN, Venkatesh , KANTIMAHANTI, Arjun Kumar
IPC分类号： H01L41/27 , H01L41/311 , H01L41/047 , H01L41/053 , H01L21/56
CPC分类号： H01L27/20 , B81B2201/0271 , B81B2207/015 , B81C1/00246 , B81C2203/0714 , B81C2203/0735 , B81C2203/0771 , H03H9/0538 , H03H9/173 , H03H9/25
摘要： This disclosure describes a monolithic integrated device having an architecture that allows the acoustic device to transduce either the surface acoustic waves or the bulk acoustic waves. The monolithic integrated device comprises a substrate layer (101) being the base of the device; an inter-layer dielectric (102) disposed on top of the substrate layer (101); an electronic circuitry substantially formed in the inter-layer dielectric (102) and supported by the substrate layer (101), the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals (204); and a piezoelectric (301) being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is a metal (204) of an upper metal layer belonging to the electronic circuitry and the bottom electrode is a metal (204) of a lower metal layer belonging to the electronic circuitry. In order to transduce bulk acoustic waves, the inter-layer dielectric is formed with a top cavity (105) above the top electrode and a bottom cavity (106) below the bottom electrode.

6. 发明授权

US11719669B2 Device for determining information of a substance in a matter 有权
公开(公告)号：US11719669B2
公开(公告)日：2023-08-08
申请号：US17180172
申请日：2021-02-19
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Arjun Kumar Kantimahanti
IPC分类号： G01N29/02 , H01L41/113
CPC分类号： G01N29/022 , H01L41/1132 , G01N2291/0256 , G01N2291/02466 , G01N2291/0423 , G01N2291/0426
摘要： A device for determining information of a substance in a matter comprising a substrate layer; an inter-layer dielectric disposed on the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and includes a plurality of metal layers with at least one metal layer being used as an inner electrode, a sensing instrument having at least one sensing component that includes a piezoelectric layer and the inner electrode that is positioned adjacent to an inner surface of the piezoelectric layer, and at least one binding layer disposed on the inter-layer dielectric for binding the substance, wherein the sensing component allows the device to determine the information of the substance upon detecting presence of the substance at the binding layer.

7. 发明申请

US20190100427A1 MONOLITHIC INTEGRATION OF PMUT ON CMOS 审中-公开
公开(公告)号：US20190100427A1
公开(公告)日：2019-04-04
申请号：US15875208
申请日：2018-01-19
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Arjun Kumar Kantimahanti
IPC分类号： B81B7/00 , B06B1/06 , G01N29/24
摘要： This disclosure describes a monolithic integrated device that comprises a substrate layer being the base of the device, an inter-layer dielectric disposed on top of the substrate layer and below a passivation layer, an electronic circuitry formed within the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals; and at least one micromachined ultrasonic transducer. Each micromachined ultrasonic transducer comprises a bottom electrode disposed on top of the passivation layer and connected to the electronic circuitry, a piezoelectric disposed on top of the bottom electrode, a top electrode disposed on top of the piezoelectric, and an elastic layer positioned on top of the top electrode. There is a cavity formed below the bottom electrode that extends from the passivation layer to a portion of the inter-layer dielectric.

8. 发明授权

US10199430B2 Monolithic integrated device 有权
公开(公告)号：US10199430B2
公开(公告)日：2019-02-05
申请号：US15494272
申请日：2017-04-21
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Wee Song Tay , Venkatesh Madhaven , Arjun Kumar Kantimahanti
IPC分类号： H01L27/20 , B81C1/00 , H03H9/25 , H03H9/17 , H03H9/05
摘要： Monolithic integrated device having an architecture that allows an acoustic device to transduce either surface acoustic waves or bulk acoustic waves, comprising: a substrate layer being the base of the device; an inter-layer dielectric disposed on top of the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers; and a piezoelectric layer being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is an upper metal layer belonging to the electronic circuitry and the bottom electrode is a lower metal layer belonging to the electronic circuitry. To transduce the bulk acoustic waves, the inter-layer dielectric is formed with a top cavity above the top electrode and a bottom cavity below the bottom electrode.

9. 发明申请

US20180151622A1 MONOLITHIC INTEGRATED DEVICE 审中-公开
公开(公告)号：US20180151622A1
公开(公告)日：2018-05-31
申请号：US15494272
申请日：2017-04-21
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Wee Song Tay , Venkatesh Madhaven , Arjun Kumar Kantimahanti
IPC分类号： H01L27/20 , H03H9/17 , H03H9/25 , B81C1/00
CPC分类号： H01L27/20 , B81B2201/0271 , B81B2207/015 , B81C1/00246 , H03H9/0538 , H03H9/173 , H03H9/25
摘要： Monolithic integrated device having an architecture that allows an acoustic device to transduce either surface acoustic waves or bulk acoustic waves, comprising: a substrate layer being the base of the device; an inter-layer dielectric disposed on top of the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers; and a piezoelectric layer being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is an upper metal layer belonging to the electronic circuitry and the bottom electrode is a lower metal layer belonging to the electronic circuitry. To transduce the bulk acoustic waves, the inter-layer dielectric is formed with a top cavity above the top electrode and a bottom cavity below the bottom electrode.

10. 发明授权

US09111676B2 Parallel stacked symmetrical and differential inductor 有权
标题翻译：并联堆叠对称和差分电感
公开(公告)号：US09111676B2
公开(公告)日：2015-08-18
申请号：US13797073
申请日：2013-03-12
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Chun Lee Ler , Mohd Hafis Mohd Ali , Yusman Yusof , Subhash Chander Rustagi
IPC分类号： H01F5/00 , H01F27/28 , H01F17/00 , H01F41/04
CPC分类号： H01F17/0013 , H01F41/041 , H01F2017/0046
摘要： A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (202, 204) disposed on an insulating layer and at least one subsequent conductive layer (206, 208) disposed on a plurality of insulating layers stacked under the at least one first conductive layer (202, 204). The at least one first conductive layer (202, 204) and each of the at least one subsequent conductive layer (206, 208) are electrically connected by a first plurality of conductive plugs (214) in a winding region (104). Each of the at least one subsequent conductive layer (206, 208) are electrically connected by a second plurality of conductive plugs (212) in a bridge region (102).
摘要翻译：公开了并联堆叠对称和差分电感器及其制造方法。平行堆叠的对称和差分电感器设置在衬底上，并且包括设置在绝缘层上的至少一个第一导电层（202,204）和布置在堆叠的多个绝缘层上的至少一个后续导电层（206,208）在所述至少一个第一导电层（202,204）下面。所述至少一个第一导电层（202,204）和所述至少一个后续导电层（206,208）中的每一个通过绕组区域（104）中的第一多个导电插塞（214）电连接。所述至少一个后续导电层（206,208）中的每一个通过桥接区域（102）中的第二多个导电插塞（212）电连接。

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