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1. 发明专利

JP2004311891A Semiconductor device 审中-公开
公开(公告)号：JP2004311891A
公开(公告)日：2004-11-04
申请号：JP2003106582
申请日：2003-04-10
申请人： Seiko Instruments Inc , Silterra Malaysia Sdn Bhd , シルテラマレーシアエスディエヌ.ビーエッチディ , セイコーインスツルメンツ株式会社
发明人： INOUE SHIGETO , WATANABE HITOMI , PAEK MIN , KIM SANG-YONG , KIM INKI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/76
CPC分类号： H01L27/0921 , H01L21/76237 , H01L21/823814 , H01L21/823878
摘要： PROBLEM TO BE SOLVED: To prevent parasitic transistor operation, and simplify and refining a process, in a semiconductor device in which a high breakdown voltage MOS transistor and a low breakdown voltage one are present mixedly.
SOLUTION: When the high breakdown voltage MOS transistor and a fine low breakdown voltage MOS transistor are mixedly mounted on a same semiconductor substrate, two STIs (shallow trench isolations) are used, an active region, where high concentration impurities are doped in the channel region of a parasitic MOS transistor, is provided between the STIs and current flowing between the source and drain of the parasitic MOS transistor is interrupted.
COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明授权

US11719669B2 Device for determining information of a substance in a matter 有权
公开(公告)号：US11719669B2
公开(公告)日：2023-08-08
申请号：US17180172
申请日：2021-02-19
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Arjun Kumar Kantimahanti
IPC分类号： G01N29/02 , H01L41/113
CPC分类号： G01N29/022 , H01L41/1132 , G01N2291/0256 , G01N2291/02466 , G01N2291/0423 , G01N2291/0426
摘要： A device for determining information of a substance in a matter comprising a substrate layer; an inter-layer dielectric disposed on the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and includes a plurality of metal layers with at least one metal layer being used as an inner electrode, a sensing instrument having at least one sensing component that includes a piezoelectric layer and the inner electrode that is positioned adjacent to an inner surface of the piezoelectric layer, and at least one binding layer disposed on the inter-layer dielectric for binding the substance, wherein the sensing component allows the device to determine the information of the substance upon detecting presence of the substance at the binding layer.

3. 发明申请

US20190100427A1 MONOLITHIC INTEGRATION OF PMUT ON CMOS 审中-公开
公开(公告)号：US20190100427A1
公开(公告)日：2019-04-04
申请号：US15875208
申请日：2018-01-19
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Arjun Kumar Kantimahanti
IPC分类号： B81B7/00 , B06B1/06 , G01N29/24
摘要： This disclosure describes a monolithic integrated device that comprises a substrate layer being the base of the device, an inter-layer dielectric disposed on top of the substrate layer and below a passivation layer, an electronic circuitry formed within the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals; and at least one micromachined ultrasonic transducer. Each micromachined ultrasonic transducer comprises a bottom electrode disposed on top of the passivation layer and connected to the electronic circuitry, a piezoelectric disposed on top of the bottom electrode, a top electrode disposed on top of the piezoelectric, and an elastic layer positioned on top of the top electrode. There is a cavity formed below the bottom electrode that extends from the passivation layer to a portion of the inter-layer dielectric.

4. 发明授权

US10322929B2 Monolithic integration of PMUT on CMOS 有权
公开(公告)号：US10322929B2
公开(公告)日：2019-06-18
申请号：US15875208
申请日：2018-01-19
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Arjun Kumar Kantimahanti
IPC分类号： B81B7/00 , B06B1/06 , G01N29/24
摘要： This disclosure describes a monolithic integrated device that comprises a substrate layer being the base of the device, an inter-layer dielectric disposed on top of the substrate layer and below a passivation layer, an electronic circuitry formed within the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals; and at least one micromachined ultrasonic transducer. Each micromachined ultrasonic transducer comprises a bottom electrode disposed on top of the passivation layer and connected to the electronic circuitry, a piezoelectric disposed on top of the bottom electrode, a top electrode disposed on top of the piezoelectric, and an elastic layer positioned on top of the top electrode. There is a cavity formed below the bottom electrode that extends from the passivation layer to a portion of the inter-layer dielectric.

5. 发明申请

US20040224488A1 Method of forming ultra shallow junctions 失效
公开(公告)号：US20040224488A1
公开(公告)日：2004-11-11
申请号：US10864030
申请日：2004-06-08
申请人： SilTerra Malaysia Sdn. Bhd.
发明人： Narayanan Meyyappan
IPC分类号： H01L021/336 , H01L021/425
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/324
摘要： The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The dopant impurities are activation annealed to form one or more doped regions extending below the surface of the semiconductor substrate. The ion energy may be varied continuously or in a stepwise manner over the time period, and may also be varied in a cyclical manner.

6. 发明申请

US20040161897A1 Semiconductor device having multiple gate oxide layers and method of manufacturing thereof 有权
标题翻译：具有多个栅极氧化物层的半导体器件及其制造方法
公开(公告)号：US20040161897A1
公开(公告)日：2004-08-19
申请号：US10367591
申请日：2003-02-13
申请人： SilTerra Malaysia Sdn. Bhd.
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
IPC分类号： H01L021/8234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.
摘要翻译：制造半导体器件的方法包括在衬底上限定第一电压区域，第二电压区域和第三电压区域。第一，第二和第三电压区域被配置为分别处理彼此不同的第一，第二和第三电压电平。形成覆盖第一，第二和第三电压区域的氮化物层。形成覆盖氮化物层的氧化物层。图案化氧化物层以暴露覆盖第一电压区域的氮化物层的一部分。使用湿蚀刻工艺去除氮化物层的暴露部分。形成覆盖第一电压区域的第一栅极氧化物层。除去覆盖第二和第三电压区域的氧化物层和氮化物层的部分。杂质被选择性地注入到第三电压区域中，同时防止在第二电压区域中提供杂质。覆盖第二电压区域的第二栅极氧化物和覆盖第三电压区域的第三栅极氧化物同时形成。第二栅极氧化物比第三栅极氧化物厚。

7. 发明授权

US10199430B2 Monolithic integrated device 有权
公开(公告)号：US10199430B2
公开(公告)日：2019-02-05
申请号：US15494272
申请日：2017-04-21
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Wee Song Tay , Venkatesh Madhaven , Arjun Kumar Kantimahanti
IPC分类号： H01L27/20 , B81C1/00 , H03H9/25 , H03H9/17 , H03H9/05
摘要： Monolithic integrated device having an architecture that allows an acoustic device to transduce either surface acoustic waves or bulk acoustic waves, comprising: a substrate layer being the base of the device; an inter-layer dielectric disposed on top of the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers; and a piezoelectric layer being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is an upper metal layer belonging to the electronic circuitry and the bottom electrode is a lower metal layer belonging to the electronic circuitry. To transduce the bulk acoustic waves, the inter-layer dielectric is formed with a top cavity above the top electrode and a bottom cavity below the bottom electrode.

8. 发明申请

US20180151622A1 MONOLITHIC INTEGRATED DEVICE 审中-公开
公开(公告)号：US20180151622A1
公开(公告)日：2018-05-31
申请号：US15494272
申请日：2017-04-21
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Mohanraj Soundara Pandian , Wee Song Tay , Venkatesh Madhaven , Arjun Kumar Kantimahanti
IPC分类号： H01L27/20 , H03H9/17 , H03H9/25 , B81C1/00
CPC分类号： H01L27/20 , B81B2201/0271 , B81B2207/015 , B81C1/00246 , H03H9/0538 , H03H9/173 , H03H9/25
摘要： Monolithic integrated device having an architecture that allows an acoustic device to transduce either surface acoustic waves or bulk acoustic waves, comprising: a substrate layer being the base of the device; an inter-layer dielectric disposed on top of the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers; and a piezoelectric layer being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is an upper metal layer belonging to the electronic circuitry and the bottom electrode is a lower metal layer belonging to the electronic circuitry. To transduce the bulk acoustic waves, the inter-layer dielectric is formed with a top cavity above the top electrode and a bottom cavity below the bottom electrode.

9. 发明授权

US09111676B2 Parallel stacked symmetrical and differential inductor 有权
标题翻译：并联堆叠对称和差分电感
公开(公告)号：US09111676B2
公开(公告)日：2015-08-18
申请号：US13797073
申请日：2013-03-12
申请人： Silterra Malaysia Sdn. Bhd.
发明人： Chun Lee Ler , Mohd Hafis Mohd Ali , Yusman Yusof , Subhash Chander Rustagi
IPC分类号： H01F5/00 , H01F27/28 , H01F17/00 , H01F41/04
CPC分类号： H01F17/0013 , H01F41/041 , H01F2017/0046
摘要： A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (202, 204) disposed on an insulating layer and at least one subsequent conductive layer (206, 208) disposed on a plurality of insulating layers stacked under the at least one first conductive layer (202, 204). The at least one first conductive layer (202, 204) and each of the at least one subsequent conductive layer (206, 208) are electrically connected by a first plurality of conductive plugs (214) in a winding region (104). Each of the at least one subsequent conductive layer (206, 208) are electrically connected by a second plurality of conductive plugs (212) in a bridge region (102).
摘要翻译：公开了并联堆叠对称和差分电感器及其制造方法。平行堆叠的对称和差分电感器设置在衬底上，并且包括设置在绝缘层上的至少一个第一导电层（202,204）和布置在堆叠的多个绝缘层上的至少一个后续导电层（206,208）在所述至少一个第一导电层（202,204）下面。所述至少一个第一导电层（202,204）和所述至少一个后续导电层（206,208）中的每一个通过绕组区域（104）中的第一多个导电插塞（214）电连接。所述至少一个后续导电层（206,208）中的每一个通过桥接区域（102）中的第二多个导电插塞（212）电连接。

10. 发明申请

US20040166698A1 Semiconductor device with dual gate oxides 有权
公开(公告)号：US20040166698A1
公开(公告)日：2004-08-26
申请号：US10377167
申请日：2003-02-26
申请人： SilTerra Malaysia Sdn. Bhd.
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Zadig Lam , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L021/8234
CPC分类号： H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.

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