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1. 发明申请

WO1986006752A1 COMBINED INTEGRATED CIRCUIT/FERROELECTRIC MEMORY DEVICE AND ION BEAM METHODS OF CONSTRUCTING SAME 审中-公开
标题翻译：组合式集成电路/电磁存储器件和离子束构造方法
公开(公告)号：WO1986006752A1
公开(公告)日：1986-11-20
申请号：PCT/US1986001032
申请日：1986-05-08
申请人： RAMTRON CORPORATION
发明人： RAMTRON CORPORATION , McMILLAN, Larry, D. , PAZ de ARAUJO, Carlos , ROHRER, George, A.
IPC分类号： C23C14/00
CPC分类号： H01G7/02 , C23C14/06 , C23C14/0623 , C23C14/46 , H01L27/11502
摘要： Methods for forming targets of ferroelectric, metal nitrate or similar material, methods for depositing such materials using ion beam techniques, and a method for forming a combined and integrated circuit/ferroelectric memory device wherein the ferroelectric material is deposited using ion beam techniques.
摘要翻译：用于形成铁电，金属硝酸盐或类似材料的靶材的方法，使用离子束技术沉积这种材料的方法，以及形成组合和集成电路/铁电存储器件的方法，其中使用离子束技术沉积铁电材料。

2. 发明申请

WO1986004447A1 METHOD OF MAKING AN INTEGRATED FERROELECTRIC DEVICE, AND DEVICE PRODUCED THEREBY 审中-公开
标题翻译：制造集成式电磁装置的方法及其生产的装置
公开(公告)号：WO1986004447A1
公开(公告)日：1986-07-31
申请号：PCT/US1986000159
申请日：1986-01-24
申请人： RAMTRON CORPORATION
发明人： RAMTRON CORPORATION , McMILLAN, Larry , PAZ DE ARAUJO, Carlos , GODFREY, Bruce , O'KEEFE, Jack , ROHRER, George, A.
IPC分类号： G11C11/22
CPC分类号： H01L27/11502
摘要： A combined integrated circuit/ferroelectric memory device using Phase III potassium nitrate as the ferroelectric material and which appears in the final device only at the crossover points of the top and bottom electrodes. The method of fabrication may use ion milling and ashing off of remaining resist. A method of making an integrated ferroelectric device comprising the steps of: (a) forming a first non-conductive layer (73) close to decode circuitry (68) of an integrated circuit (60); (b) forming channels (74-80) through layer (73); (c) forming trenches (89-95) in layer (73) next to channels (74-80); (d) completely filling channels (74-80) and partially filling trenches (89-95) with a first metal (98); (e) filling voids in trenches (89-95) with a second non-conductive material (99); (f) planarizing the upper surface (100) of layer (73), metal (98), and material (99); (g) forming a second non-conductive layer (102) on surface (100); (h) forming passages (103-113) through layer (102) next to trenches (89-95); (i) forming a ferroelectric layer (116) to overlie layer (102) and part of metal (98); (j) forming a second metal (117) to overlie layer (116); (k) removing undesired parts of metal (117), layer (116), and layer (102); (l) forming a third metal layer to overlie the remainder (121) of metal (117) and of layer (102), and exposed portions (120) of layer (116) and of first metal (98); and (m) removing undesired portions of the third metal layer.
摘要翻译：使用III型硝酸钾作为铁电材料并且仅在顶部和底部电极的交叉点处出现在最终装置中的组合集成电路/铁电存储器件。制造方法可以使用离子铣削和剩余抗蚀剂的灰化。一种制造集成铁电器件的方法，包括以下步骤：（a）形成靠近集成电路（60）的解码电路（68）的第一非导电层（73）; （b）通过层（73）形成通道（74-80）; （c）在通道（74-80）旁边的层（73）中形成沟槽（89-95）; （d）用第一金属（98）完全填充通道（74-80）和部分填充沟槽（89-95）; （e）用第二非导电材料（99）填充沟槽（89-95）中的空隙; （f）对层（73）的上表面（100），金属（98）和材料（99）进行平面化; （g）在表面（100）上形成第二非导电层（102）; （h）在沟槽（89-95）旁边通过层（102）形成通道（103-113）; （i）形成铁电层（116）以覆盖层（102）和部分金属（98）; （j）形成覆盖在层（116）上的第二金属（117）; （k）去除不需要的金属部分（117），层（116）和层（102）; （1）形成第三金属层以覆盖金属（117）和层（102）的剩余部分（121）和层（116）和第一金属（98）的暴露部分（120）; 和（m）去除所述第三金属层的不期望部分。

3. 发明授权

US5170242A Reaction barrier for a multilayer structure in an integrated circuit 失效
标题翻译：集成电路中多层结构的反应势垒
公开(公告)号：US5170242A
公开(公告)日：1992-12-08
申请号：US698841
申请日：1991-05-10
申请人： E. Henry Stevens , Masahiro Maekawa
发明人： E. Henry Stevens , Masahiro Maekawa
IPC分类号： H01L21/285 , H01L23/532 , H01L29/43 , H01L29/45
CPC分类号： H01L21/28518 , H01L21/28568 , H01L23/53223 , H01L29/43 , H01L29/456 , H01L2924/0002
摘要： A reaction barrier is formed at an interface region between adjacent layers of a multilayer composite integrated circuit by implanting one or more active ionic species at energies effective to place the ionic species at or near the interface. A further step may include annealing the structure formed above to promote efficacy of the reaction barrier.
摘要翻译：在多层复合集成电路的相邻层之间的界面区域处形成反应势垒，通过在有效将离子物质置于界面处或附近的能量处注入一种或多种活性离子物质。另外的步骤可以包括退火上述形成的结构以促进反应势垒的功效。

4. 发明授权

US4914627A One transistor memory cell with programmable capacitance divider 失效
标题翻译：一个具有可编程电容分压器的晶体管存储单元
公开(公告)号：US4914627A
公开(公告)日：1990-04-03
申请号：US292776
申请日：1989-01-03
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
摘要翻译：偏振器用作可编程电容分压器。两个铁电电容器串联耦合以形成公共节点和两个极端极。两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。电容分压器根据数据进行编程。一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。相同的分配器布置可在易失性和非易失性模式下操作。通过使用PZT作为54:46摩尔比的电介质来改善。

5. 发明授权

US4853893A Data storage device and method of using a ferroelectric capacitance divider 失效
标题翻译：数据存储装置及使用铁电电容分压器的方法
公开(公告)号：US4853893A
公开(公告)日：1989-08-01
申请号：US69389
申请日：1987-07-02
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Later, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.

6. 发明授权

US5117177A Reference generator for an integrated circuit 失效
标题翻译：用于集成电路的参考发生器
公开(公告)号：US5117177A
公开(公告)日：1992-05-26
申请号：US644904
申请日：1991-01-23
申请人： S. Sheffield Eaton, Jr.
发明人： S. Sheffield Eaton, Jr.
IPC分类号： G05F3/24 , H02M3/07
CPC分类号： H02M3/07 , G05F3/247
摘要： A voltage reference generated for an integrated circuit which produces a source of reference voltage which is self-compensated for variations in operating voltage (V.sub.cc) or in transistor threshold voltages (V.sub.T). The circuit uses a voltage divider coupled between V.sub.cc and ground and has first and second FET transistors. A faced control circuit is coupled to control the conductivity of the first transistor, and the second control circuit is coupled to control the conductivity of the second transistor. The first control circuit produces a control voltage which varies as a function of variations in V.sub.cc, while the second control circuit also provides a control voltage wherein variations are a function of variations in V.sub.cc, but in an opposite direction. Hence, the second control voltage is configured so that variations in V.sub.cc cause the second transistor to compensate for changes in operation of the first transistor, so that the reference voltage remains substantially constant.
摘要翻译：产生用于集成电路的电压基准，其产生对工作电压（Vcc）或晶体管阈值电压（VT）中的变化进行自补偿的参考电压源。该电路使用耦合在Vcc和地之间的分压器，并具有第一和第二FET晶体管。耦合面对的控制电路以控制第一晶体管的导电性，并且第二控制电路被耦合以控制第二晶体管的导电性。第一控制电路产生作为Vcc变化的函数而变化的控制电压，而第二控制电路还提供控制电压，其中变化是Vcc变化但是在相反方向上的变化。因此，第二控制电压被配置为使得Vcc的变化使得第二晶体管补偿第一晶体管的操作变化，使得参考电压基本保持不变。

7. 发明授权

US5104822A Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method 失效
标题翻译：使用该方法创建自对准的非图案接触区域和堆叠电容器的方法
公开(公告)号：US5104822A
公开(公告)日：1992-04-14
申请号：US559466
申请日：1990-07-30
申请人： Douglas B. Butler
发明人： Douglas B. Butler
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/92
CPC分类号： H01L27/10805 , H01L28/40 , Y10S257/90
摘要： In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.

8. 发明授权

US5024964A Method of making ferroelectric memory devices 失效
标题翻译：制备铁电存储器件的方法
公开(公告)号：US5024964A
公开(公告)日：1991-06-18
申请号：US793186
申请日：1985-10-31
申请人： George A. Rohrer , Larry D. McMillin
发明人： George A. Rohrer , Larry D. McMillin
IPC分类号： C23C14/06 , H01G7/02
CPC分类号： H01G7/02 , C23C14/06 , H01G7/025
摘要： A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 25,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.
摘要翻译：公开了单片半导体集成电路 - 铁电体器件及其制造方法。铁电体器件优选由设置在位于铁电层的相对表面上的电触点之间的稳定的铁电硝酸钾层组成。铁电层的厚度小于110微米，优选在100埃至25,000埃的范围内。制造整体式结构的方法是多级的，特别适用于在半导体集成电路上制造硝酸钾铁电存储器。

9. 发明授权

US5075817A Trench capacitor for large scale integrated memory 失效
标题翻译：用于大规模集成存储器的TRENCH电容器
公开(公告)号：US5075817A
公开(公告)日：1991-12-24
申请号：US542573
申请日：1990-06-22
申请人： Douglas B. Butler
发明人： Douglas B. Butler
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , Y10T29/435
摘要： A trench capacitor which has a plurality of capacitor plates separated by a dielectric within a trench on a substrate. A plate located closest to the wall of the trench may be a field shield and tied everywhere to ground. The other plate may be polysilicon. Said other plate may be tied to a source of variable potential. A plurality of sacrificial layers are established over the structure and the structure thus formed is then patterened and etched. A pass transistor is formed adjacent to the trench capacitor, and a connecting layer is established connecting the other plate of the trench capacitor to the source/drain region of the pass transistor. The connecting layer makes electrical contact to the other capacitor plate and source/drain of the pass transistor and is insulated from other layers in the capacitor and pass transistor. Bit lines and word lines can then be added, as known in the art.

10. 发明授权

US4918654A SRAM with programmable capacitance divider 失效
标题翻译：具有可编程电容分压器的SRAM
公开(公告)号：US4918654A
公开(公告)日：1990-04-17
申请号：US292818
申请日：1989-01-03
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
摘要翻译：偏振器用作可编程电容分压器。两个铁电电容器串联耦合以形成公共节点和两个极端极。两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。电容分压器根据数据进行编程。一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。相同的分配器布置可在易失性和非易失性模式下操作。通过使用PZT作为54:46摩尔比的电介质来改善。

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