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1. 发明专利

JPH08202575A AUTOMATIC CLOCK-VERIFIER SELECTION METHOD IN REPROGRAMMABLE-HARDWARE EMULATION SYSTEM 失效
公开(公告)号：JPH08202575A
公开(公告)日：1996-08-09
申请号：JP21729595
申请日：1995-08-25
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： PINNSAN TSUEN
IPC分类号： G01R31/28 , G01R31/00 , G06F1/06 , G06F1/08 , G06F11/22 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To easily specify an actual clock tester by deciding the latent speed of respective nets inside the net list of a user. SOLUTION: An operation is performed by initializing the speed of the respective nets to '0' inside the net list. Then, by setting the speed of a clock source specified by the user to '1' first, a latent clock net is marked. Then, after the speed of the output of respective logic elements 58 is set to '1' in the case that one of the input is provided with the speed of '1', the maximum speed of the respective nets is calculated. Thereafter, the trimming processing of the net list is performed by tracing back from respective internal clock signals 30 to the clock source. Then, the net list inputted to the logic element inside the net list slower than the maximum speed of any nets inputted to the logic element is marked as a latent clock tester.

2. 发明专利

JPH0844787A MULTIPORT MEMORY EMULATION USING TAG REGISTER 失效
公开(公告)号：JPH0844787A
公开(公告)日：1996-02-16
申请号：JP6654995
申请日：1995-03-24
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： TOOMASU BII HIYUAN
IPC分类号： G11C11/401 , G06F17/50 , G11C8/16
摘要： PURPOSE: To emulate a multiport memory circuit by using memory resource of plural programmable logic elements. CONSTITUTION: First, this emulation method generates a net list of read port memory array which has plural storage places and generates a net list of write port memory array by duplicating the net list of the read port memory array plural times in memory resource of programmable logic elements. Next, the method duplicates the net list of the write port memory array plural times, programs the memory resource to constitute plural write port memory arrays, furthermore, writes data in specific storage places of each write port memory array in a specific write port memory array, and attaches a tag which shows that data was written newly to the storage places in which data is written newly.

3. 发明专利

FR2724030A1 PROCEDE DE SELECTION AUTOMATIQUE DE QUALIFICATEURS D'IMPULSIONS D'HORLOGE DANS DES SYSTEMES D'EMULATION DE MATERIEL REPROGRAMMABLE 未知
公开(公告)号：FR2724030A1
公开(公告)日：1996-03-01
申请号：FR9510101
申请日：1995-08-25
申请人： QUICKTURN DESIGN SYSTEMS INC , QUICKTURN DESIGN SYSTEMS INC
发明人： TZENG PING SAN , TZENG PING SAN
IPC分类号： G01R31/00 , G06F1/06 , G01R31/28 , G06F1/08 , G06F11/22 , G06F17/50 , G06F19/00
摘要： L'invention concerne un procédé d'identification de qualificateurs d'impulsions d'horloge potentiels dans la description d'une liste de réseaux d'un circuit intégré, la liste de réseaux comprenant des éléments logiques. Le procédé comprend les étapes d'initialisation (100) de chaque réseau de la liste de réseaux à une vitesse de zéro, d'identification (105) de tous les réseaux d'impulsions d'horloge potentiels de telle sorte que tous les signaux ayant un trajet vers une source d'impulsions d'horloge aient une vitesse de un, de calcul (120-145) de la vitesse maximum de chaque réseau de sortie de chacun des éléments logiques dans la liste de réseaux, et de marquage (150-175) en tant que qualificateur d'impulsions d'horloge potentiel de tout réseau de la liste de réseaux qui est introduit dans les éléments logiques dans la liste de réseaux et qui est plus lent que la vitesse maximum de tout réseau et qui est introduit dans les éléments logiques.

4. 发明申请

WO2006133149A3 METHOD FOR ANALYZING POWER CONSUMPTION OF CIRCUIT DESIGN USING HARDWARE EMULATION 审中-公开
标题翻译：使用硬件仿真分析电路设计功耗的方法
公开(公告)号：WO2006133149A3
公开(公告)日：2007-03-22
申请号：PCT/US2006021857
申请日：2006-06-05
申请人： QUICKTURN DESIGN SYSTEMS INC , TUNG TUNG-SUN , LIN TSAIR-CHIN , ZHU BING
发明人： TUNG TUNG-SUN , LIN TSAIR-CHIN , ZHU BING
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F2217/78
摘要： The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of "events" which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.
摘要翻译：这里描述的发明是在预期应用环境和软件下使用基于硬件的功能验证系统来模拟被测设计（DUT）的方法来记录或导出DUT的所有电路的转换活动，然后计算在兴趣期间的全部或部分功耗。感兴趣的时期由用户根据DUT的任意状态的“事件”定义。此外，用户可以指定事件之间所需的子划分的数量，从而改变功耗曲线的表观分辨率。

5. 发明申请

WO0241167A3 METHOD AND APPARATUS FOR DYNAMICALLY TESTING ELECTRICAL INTERCONNECT 审中-公开
标题翻译：用于动态测试电气互连的方法和装置
公开(公告)号：WO0241167A3
公开(公告)日：2003-09-12
申请号：PCT/US0150837
申请日：2001-10-19
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： QUAYLE BARTON , SAMPLE STEPHEN P
IPC分类号： G01R31/28 , G06F17/50 , G01R31/3185
CPC分类号： G01R31/2853 , G06F17/5027
摘要： A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.
摘要翻译：公开了一种硬件仿真系统，其通过将多个设计信号时分多路复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。逻辑器件和互连器件互连在一起，使得多个设计信号共享公共输入/输出引脚和电路板迹线。还公开了一种用于硬件仿真系统的逻辑分析仪。执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。还公开了用于动态测试集成电路之间的互连的方法。

6. 发明申请

WO2002063507A3 HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZED FOR EFFICIENT DATA LOADING AND UNLOADING 审中-公开
公开(公告)号：WO2002063507A3
公开(公告)日：2002-08-15
申请号：PCT/US2001/050388
申请日：2001-10-19
申请人： QUICKTURN DESIGN SYSTEMS, INC.
发明人： OHKAMI, Takahide
IPC分类号： G06F17/50
摘要： A system is prvided to increase the accessibility of registers and memories in a user's design undergoing functional verificationin a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and ahardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

7. 发明申请

WO2006133149A2 SYSTEM AND METHOD FOR ANALYZING POWER CONSUMPTION OF ELECTRONIC DESIGN UNDERGOING EMULATION OR HARDWARE BASED ON SIMULATION ACCELERATION 审中-公开
标题翻译：基于模拟加速分析仿真或硬件的电子设计功耗分析系统与方法
公开(公告)号：WO2006133149A2
公开(公告)日：2006-12-14
申请号：PCT/US2006/021857
申请日：2006-06-05
申请人： QUICKTURN DESIGN SYSTEMS, INC. , TUNG, Tung-Sun , LIN, Tsair-Chin , ZHU, Bing
发明人： TUNG, Tung-Sun , LIN, Tsair-Chin , ZHU, Bing
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F2217/78
摘要： The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of "events" which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.
摘要翻译：这里描述的发明是使用基于硬件的功能验证系统在预期的应用环境和软件下模拟被测设计（DUT）来记录或导出DUT的所有电路的转换活动的方法，然后计算在兴趣期间的全部或部分功耗。感兴趣的时期由用户根据DUT的任意状态的“事件”定义。此外，用户可以指定事件之间所需的子分割的数量，从而改变功耗简档的视在分辨率。

8. 发明申请

WO2002063507A2 HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZED FOR EFFICIENT DATA LOADING AND UNLOADING 审中-公开
标题翻译：使用基于分组的协议逻辑的硬件辅助设计验证系统合成有效数据加载和卸载
公开(公告)号：WO2002063507A2
公开(公告)日：2002-08-15
申请号：PCT/US2001/050388
申请日：2001-10-19
申请人： QUICKTURN DESIGN SYSTEMS, INC.
发明人： OHKAMI, Takahide
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system is prvided to increase the accessibility of registers and memories in a user's design undergoing functional verificationin a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and ahardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.
摘要翻译：在硬件辅助设计验证系统中，通过系统进行功能验证的用户设计，提供了一种增加寄存器和存储器可访问性的系统。在逻辑仿真期间，基于分组的协议用于在主机工作站和硬件加速器之间执行数据传输操作，用于在目标设计（DUV）中将数据加载到数据寄存器和存储器中并从其中卸载数据。该方法和装置将接口逻辑合成到DUV中以提供对在硬件加速器的辅助下模拟的目标DUV中的寄存器和存储器的更大访问。

9. 发明专利

DE69737757T2 未知
公开(公告)号：DE69737757T2
公开(公告)日：2008-01-31
申请号：DE69737757
申请日：1997-02-05
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： CHILTON JOHN E , SARNO TONY R , SCHAEFER INGO
IPC分类号： G06F11/26 , G06F11/22 , G06F17/50
摘要： A system and method for emulating memory designs (195) is described. The system includes a time sliced logic emulator (150). The time sliced logic emulator (150) emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs (195) included in the target design. The system includes an emulation memory (180). The memory designs (195) are mapped to the emulation memory (180) via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories. Thus over multiple time slices, the system can emulate many different types of memories.

10. 发明专利

DE19808988B4 未知
公开(公告)号：DE19808988B4
公开(公告)日：2007-05-24
申请号：DE19808988
申请日：1998-03-03
申请人： QUICKTURN DESIGN SYSTEMS INC N
发明人： SARNO TONY R , SCHAEFER INGO , CHILTON JOHN E , PAPAMARCOS MARK S , BLANDING CURTIS J
IPC分类号： G06F11/22 , G06F17/50 , G01R31/317 , G06F11/26 , G11C29/00
摘要： A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.

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