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1. 发明授权

US4827251A Display control system with control of background luminance or color data 失效
标题翻译：显示控制系统，控制背景亮度或颜色数据
公开(公告)号：US4827251A
公开(公告)日：1989-05-02
申请号：US008316
申请日：1987-01-29
申请人： Hiroshi Aoki , Kenichi Naka
发明人： Hiroshi Aoki , Kenichi Naka
IPC分类号： G06F3/153 , G09G1/00 , G09G1/26 , G09G1/28 , G09G5/00 , G09G5/02
CPC分类号： G09G5/026
摘要： A display control system with a control of background luminance or color data applicable for a personal computer with a paper-white type display device includes a character video signal generation unit, a background luminance setting register, a video enable signal generation unit, a video signal priority unit, and a video signal synthesis unit. A first video enable signal from the video enable signal generation unit controls the supply of the video signals to the video signal priority unit. A second video enable signal from the video enable signal generation unit controls a display of background in a background luminance tone or color designated by the background luminance setting register for an intermediate range when the character video signal is absent.
摘要翻译：具有对具有纸白型显示装置的个人计算机可应用的背景亮度或颜色数据的显示控制系统包括字符视频信号生成单元，背景亮度设置寄存器，视频使能信号生成单元，视频信号优先级单位和视频信号合成单元。来自视频使能信号生成单元的第一视频使能信号控制向视频信号优先级单元提供视频信号。来自视频使能信号生成单元的第二视频使能信号控制当不存在字符视频信号时的中间范围的背景亮度设置寄存器指定的背景亮度色调或颜色的背景显示。

2. 发明授权

US4849747A Display data transfer control apparatus applicable for display unit 失效
标题翻译：适用于显示单元的显示数据传送控制装置
公开(公告)号：US4849747A
公开(公告)日：1989-07-18
申请号：US928012
申请日：1986-11-07
申请人： Shinji Ogawa , Haruhiko Tsuchiya , Tsutomu Araki , Hiroshi Aoki , Hiroshi Yamamoto
发明人： Shinji Ogawa , Haruhiko Tsuchiya , Tsutomu Araki , Hiroshi Aoki , Hiroshi Yamamoto
IPC分类号： G06F3/153 , G09G5/24 , G09G5/30 , G09G5/393
CPC分类号： G09G5/30 , G09G5/393
摘要： Disclosed is a display data transfer control apparatus in which a line control memory which can preset raster count data for modifying, in units of lines, an address of a main storage storing a character font to be displayed and character attribute data are provided, and a transfer line in the character font is determined for each line transfer in a DMA transfer sequence, so that, e.g., multi font control, character vertical elongation control, and ruled line vertical extension control, as well as processing character attributes such as an underline and overline, can be realized in the DMA transfer sequence.
摘要翻译：公开了一种显示数据传送控制装置，其中，提供可以预设用于以行为单位修改存储要显示的字符字体的主存储器的地址和字符属性数据的光栅计数数据的行控制存储器，以DMA传送序列中的每行传输确定字符字体中的传输行，以便例如多字体控制，字符垂直延伸控制和规则垂直扩展控制，以及处理字符属性，例如下划线和上线，可以在DMA传输顺序中实现。

3. 发明授权

US4602330A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US4602330A
公开(公告)日：1986-07-22
申请号：US685613
申请日：1984-12-28
申请人： Fumihiro Ikeya
发明人： Fumihiro Ikeya
IPC分类号： G06F9/34 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0292
摘要： In a data processor for handling data comprising words of n-bits, a plurality of (n+m)-bit registers is provided for use as general purpose and address expansion registers, and effective addresss of (n+m)-bits are generated by adding addresses having n bits and provided in the instructions with the (n+m)-bit content of registers designated by the instructions. Thus, a data processor can be designed so as to have an expandable address bit length and flexible addressing with little additional hardware.
摘要翻译：在用于处理包括n位字的数据的数据处理器中，提供多个（n + m）位寄存器用作通用和地址扩展寄存器，并且生成（n + m）个位的有效地址通过添加具有n位的地址并在指令中提供由指令指定的寄存器的（n + m）位内容。因此，可以将数据处理器设计成具有可扩展的地址位长度和灵活的寻址，而少量的附加硬件。

4. 外观设计

USD280900S Printer 失效
公开(公告)号：USD280900S
公开(公告)日：1985-10-08
申请号：US459941
申请日：1983-01-21
申请人： Tomoki Tsumura , Hiroshi Maruoka , Toshio Asaji , Mitsuru Yamamoto
设计人： Tomoki Tsumura , Hiroshi Maruoka , Toshio Asaji , Mitsuru Yamamoto

5. 发明公开

EP0025801A1 ACCESS SYSTEM FOR MEMORY MODULES 失效
标题翻译：准入制度的内存模块。
公开(公告)号：EP0025801A1
公开(公告)日：1981-04-01
申请号：EP80900611.7
申请日：1980-03-28
申请人： PANAFACOM LIMITED
发明人： IMURA, Takao , KOYANAGI, Shigeru , JODA, Yoshihiro
IPC分类号： G06F13/00 , G11C8/00
CPC分类号： G06F12/0215
摘要： An access system for memory modules (47'-0 to 47'-31) by using an effective address which consists of more than two portions wherein one portion is determined later than other portions. The system comprises first means (41-1) for storing one portion in the present effective address, second means (41-2) for storing other portions in the present effective address third means (41-3) for storing the one portion in a previous effective address, and means (48) for comparing the content of the first means with the content of the third means. In the system, practical access to the memory modules is performed before the whole of the present effective address is determined.

6. 发明授权

US4803618A Multiprocessor system having common memory 失效
标题翻译：具有公共存储器的多处理器系统
公开(公告)号：US4803618A
公开(公告)日：1989-02-07
申请号：US819658
申请日：1986-01-17
申请人： Noboru Ita , Shigeru Mitsugi
发明人： Noboru Ita , Shigeru Mitsugi
IPC分类号： G06F12/14 , G06F9/52 , G06F12/00 , G06F15/16 , G06F15/167 , G06F15/177 , G06F13/00
CPC分类号： G06F15/167
摘要： A plurality of processors use a common memory under a time division control mode by way of a time division data bus. In the multiprocessor system, flip-flops are mounted for holding respective write permission flags. Also, a logic gate is employed, operative to allow the processor to write data in the common memory when both the write permission flag and the write request signal from the processor are generated simultaneously. Further, multiplexers are used so that the write operation can be achieved under the time division control mode.
摘要翻译：多个处理器通过时分数据总线在时分控制模式下使用公共存储器。在多处理器系统中，安装了用于保持各自的写许可标志的触发器。此外，采用逻辑门，当两者同时产生来自处理器的写允许标志和写请求信号时，可操作地允许处理器将数据写入公共存储器。此外，使用多路复用器，使得可以在时分控制模式下实现写入操作。

7. 外观设计

USD279187S Computer 失效
公开(公告)号：USD279187S
公开(公告)日：1985-06-11
申请号：US460637
申请日：1983-01-24
申请人： Tomoki Tsumura , Hiroshi Maruoka , Toshio Asaji , Mitsuru Yamamoto
设计人： Tomoki Tsumura , Hiroshi Maruoka , Toshio Asaji , Mitsuru Yamamoto

8. 发明授权

US4334269A Data processing system having an integrated stack and register machine architecture 失效
标题翻译：具有集成堆栈和注册机架构的数据处理系统
公开(公告)号：US4334269A
公开(公告)日：1982-06-08
申请号：US92859
申请日：1979-11-09
申请人： Yoshihisa Shibasaki , Ken Sakamura , Waichi Sakamae , Koichi Nakano , Hideo Aiso
发明人： Yoshihisa Shibasaki , Ken Sakamura , Waichi Sakamae , Koichi Nakano , Hideo Aiso
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34 , G06F9/44 , G06F13/00
CPC分类号： G06F9/30189 , G06F9/30138 , G06F9/30163
摘要： A data processing system includes three resources, i.e., a memory, a general purpose register file having a plurality of elements and a stack having a top. The system further includes a first mechanism for making the top of the stack correspond to at least one of the elements in the general purpose register and a second mechanism for controlling the operation of the stack. When the element to which the top of the stack corresponds is specified in an instruction register of the system, the top of the stack is selected to be accessed by the first mechanism and the operation of the stack is controlled by the second mechanism.
摘要翻译：数据处理系统包括三个资源，即存储器，具有多个元件的通用寄存器文件和具有顶部的堆栈。该系统还包括用于使堆叠的顶部对应于通用寄存器中的至少一个元件的第一机构和用于控制堆叠的操作的第二机构。当堆栈的顶部对应的元件在系统的指令寄存器中被指定时，堆叠的顶部被选择以被第一机制访问，并且堆栈的操作由第二机制控制。

9. 发明授权

US4128881A Shared memory access control system for a multiprocessor system 失效
标题翻译：用于多处理器系统的共享内存访问控制系统
公开(公告)号：US4128881A
公开(公告)日：1978-12-05
申请号：US658853
申请日：1976-02-18
申请人： Mitsuru Yamamoto , Jun Arai , Takao Isogawa , Isamu Hasebe
发明人： Mitsuru Yamamoto , Jun Arai , Takao Isogawa , Isamu Hasebe
IPC分类号： G06F15/16 , G06F12/00 , G06F12/02 , G06F13/24 , G06F15/167 , G06F9/20 , G06F13/00
CPC分类号： G06F13/24
摘要： In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor.A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.
摘要翻译：在具有多个处理器的多处理器系统中，每个处理器具有相同的结构，每个处理器内部配备有固定地址供应源，其产生用于通过共同连接的总线访问公共存储器单元的非唯一固定地址，以及顺序状态指示当相对于处理器发生特殊条件（例如，中断）时产生逻辑“1”或“0”同步信号的信号发生器。

10. 发明授权

US4896257A Computer system having virtual memory configuration with second computer for virtual addressing with translation error processing 失效
标题翻译：具有虚拟存储器配置的计算机系统，具有用于具有翻译错误处理的虚拟寻址的第二计算机
公开(公告)号：US4896257A
公开(公告)日：1990-01-23
申请号：US275598
申请日：1988-11-23
申请人： Kazuhiko Ikeda , Naoki Koizumi
发明人： Kazuhiko Ikeda , Naoki Koizumi
IPC分类号： G06F11/00 , G06F12/10 , G06F12/14
CPC分类号： G06F12/1027
摘要： A computer system including a first computer unit processing user's tasks, a second computer unit performing a halt operation for a virtual memory access, a main memory storing a plurality of virtual accessing data, a buffer memory unit temporarily storing a part of the virtual accessing data and having a faster operation time than that of the main memory, and a control unit controlling the above. The buffer memory unit receives a virtual memory address from the first computer unit and outputs a corresponding actual memory address for accessing the main memory. The control unit includes first and second latches and outputs a bi-state interruption signal and a multilevel interruption signal in response to states of the first and second latch circuits. The first latch is set when a corresponding virtual access data is invalid so that the second computer unit is operated in response to the bi-state interruption signal to store a corresponding virtual access data in the main memory unit into the buffer memory unit. The second latch is set when the corresponding virtual access data in the main memory unit to be stored into the buffer memory unit is erroneous so that the multilevel interruption signal is output from the control unit to the first computer unit to terminate the operation of the virtual memory access.
摘要翻译：一种计算机系统，包括处理用户任务的第一计算机单元，执行虚拟存储器访问的停止操作的第二计算机单元，存储多个虚拟访问数据的主存储器，临时存储虚拟访问数据的一部分的缓冲存储器单元并且具有比主存储器更快的操作时间，以及控制上述的控制单元。缓冲存储器单元从第一计算机单元接收虚拟存储器地址，并输出对应的实际存储器地址以访问主存储器。控制单元包括第一和第二锁存器，并响应于第一和第二锁存电路的状态输出双态中断信号和多电平中断信号。当相应的虚拟访问数据无效时，第一锁存器被设置，使得响应于双态中断信号操作第二计算机单元，以将主存储器单元中的相应虚拟访问数据存储到缓冲存储器单元中。当存储在缓冲存储器单元中的主存储器单元中的对应虚拟访问数据是错误的时，第二锁存器被设置为使得多级中断信号从控制单元输出到第一计算机单元以终止虚拟内存访问。

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