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1. 发明申请

WO0062182A3 PARALLEL DATA PROCESSING APPARATUS 审中-公开
标题翻译：并行数据处理设备
公开(公告)号：WO0062182A3
公开(公告)日：2001-04-12
申请号：PCT/GB0001332
申请日：2000-04-07
申请人： PIXELFUSION LTD , STUTTARD DAVE , WILLIAMS DAVE , O DEA EAMON , FAULDS GORDON , RHODES JOHN , CAMERON KEN , ATKIN PHIL , WINSER PAUL , DAVID RUSSELL , MCCONNELL RAY , DAY TIM , GREER TREY
发明人： STUTTARD DAVE , WILLIAMS DAVE , O'DEA EAMON , FAULDS GORDON , RHODES JOHN , CAMERON KEN , ATKIN PHIL , WINSER PAUL , DAVID RUSSELL , MCCONNELL RAY , DAY TIM , GREER TREY
IPC分类号： G06F15/16 , G06F7/52 , G06F9/38 , G06F9/46 , G06F11/00 , G06F15/00 , G06F15/177 , G06F15/76 , G06F15/80
CPC分类号： G06F9/3001 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3838 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F15/8007 , G06F15/8015 , G06T1/20
摘要： A data processing apparatus comprises a SIMD (single instruction multiple data) array (10) of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items.
摘要翻译：数据处理装置包括处理元件的SIMD（单指令多数据）阵列（10）。处理元件可操作地分成多个处理块，处理块可操作以处理各组数据项。

2. 发明申请

WO0017759A3 COMPUTER SYSTEM COMPRISING LATENCY TOLERANT AND INTOLERANT MODULES 审中-公开
标题翻译：包含容忍和非绝食模块的计算机系统
公开(公告)号：WO0017759A3
公开(公告)日：2000-08-10
申请号：PCT/GB9903089
申请日：1999-09-16
申请人： PIXELFUSION LTD , PHELPS RICHARD CARL , WINSER PAUL ANTHONY
发明人： PHELPS RICHARD CARL , WINSER PAUL ANTHONY
IPC分类号： G06F12/06 , G06F13/16 , G06F13/362 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4059 , G06F12/0661 , G06F13/1642 , G06F13/362 , G06F13/4004 , G06F13/4031 , G06F13/404
摘要： Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
摘要翻译：用于计算机系统的装置包括总线架构，连接到总线架构的多个模块，至少一个模块是等待时间容忍的，以及至少一个模块是延迟不耐受的。总线架构包括具有连接到其上的延迟不耐受模块的主总线（3），具有连接到其上的等待时间容限模块的辅助总线（4）和互连主总线和辅助总线的主副总线接口模块（5）。

3. 发明专利

GB2341771B Address decoding and access control for bus modules 未知
公开(公告)号：GB2341771B
公开(公告)日：2003-10-22
申请号：GB9820428
申请日：1998-09-18
申请人： PIXELFUSION LTD , CLEARSPEED TECHNOLOGY LTD
发明人： PHELPS RICHARD CARL , WINSER PAUL ANTHONY
IPC分类号： G06F12/06 , G06F13/40 , H04L12/403 , G06F13/364 , H04L12/40

4. 发明专利

GB2341767B Bus arbitration 未知
公开(公告)号：GB2341767B
公开(公告)日：2003-10-22
申请号：GB9820415
申请日：1998-09-18
申请人： PIXELFUSION LTD , CLEARSPEED TECHNOLOGY LTD
发明人： PHELPS RICHARD CARL , WINSER PAUL ANTHONY
IPC分类号： G06F13/362 , H04L12/403 , G06F13/364 , G06F13/40 , H04L12/40

5. 发明专利

GB2362035B Forming electrical/mechincal connections 未知
公开(公告)号：GB2362035B
公开(公告)日：2002-08-14
申请号：GB0028595
申请日：2000-11-23
申请人： PIXELFUSION LTD , CLEARSPEED TECHNOLOGY LTD , WAKEFIELD ELWYN PAUL MICHAEL
发明人： WAKEFIELD ELWYN PAUL MICHAEL
IPC分类号： H01L21/48 , H01L21/60 , H05K3/40 , H01L21/607 , B23K20/00 , H05K3/32

6. 发明专利

GB2356718A Data processing 未知
公开(公告)号：GB2356718A
公开(公告)日：2001-05-30
申请号：GB0015766
申请日：2000-06-27
申请人： PIXELFUSION LTD
发明人： CAMERON KEN , O'DEA EAMON
IPC分类号： G06T15/40 , G06F15/80

7. 发明专利

GB0103679D0 Network processing-network output processor (NOP) 未知
公开(公告)号：GB0103679D0
公开(公告)日：2001-03-28
申请号：GB0103679
申请日：2001-02-14
申请人： PIXELFUSION LTD

8. 发明专利

GB0103672D0 Network processing-the core 未知
公开(公告)号：GB0103672D0
公开(公告)日：2001-03-28
申请号：GB0103672
申请日：2001-02-14
申请人： PIXELFUSION LTD

9. 发明专利

GB2352381A Processing graphical data 未知
公开(公告)号：GB2352381A
公开(公告)日：2001-01-24
申请号：GB0006986
申请日：2000-03-22
申请人： PIXELFUSION LTD
发明人： CAMERON KEN , O'DEA EAMON
IPC分类号： G06T15/40 , G06T15/00
摘要： Method of processing image data to be displayed having a plurality of pixels comprising: a. defining a data queue having a predetermined number of locations therein; b. defining the depth value of the most visible opaque primitive to be displayed at the pixel; c. defining the depth value of the most visible transparent primitive to be displayed at the pixel; d. receiving fragment information belonging to an image to be displayed at the pixel, and; e. determining whether it relates to a visible image with respect to the opaque depth value, and discarding it if it does not, otherwise; f. determining if it belongs an opaque image or to a transparent image; g. if opaque: 1. updating the opaque depth value to equal the fragment depth value, 2. determining if the fragment information is visible with reference to the transparent depth value; and if so; 3. clearing the queue locations and updating the transparent depth values to equal the fragment depth value; h. if transparent and visible with respect to the transparent depth value, updating the transparent depth value to equal the fragment depth value; i. storing the fragment data in the next available queue location; j. repeating steps d. to i. for new fragment info. until the queue is full, or until no further fragment info. is available; k. sorting the entries in the queue in depth value order; and processing in turn fragment info. stored in the queue locations to produce respective pixel display values.

10. 发明专利

GB2348977A Parallel data processing systems with a SIMD array 未知
公开(公告)号：GB2348977A
公开(公告)日：2000-10-18
申请号：GB9908211
申请日：1999-04-09
申请人： PIXELFUSION LTD
发明人： GREER TREY , RHODES JOHN , MCCONNELL RAY , WINSER PAUL
IPC分类号： G06F9/38 , G06F15/80
摘要： A method of processing data items using a SIMD (single instruction multiple data) array (10) of processing elements comprises supplying a common instruction to all of the processing elements in the array (10); and supplying respective data items to the processing elements such that each processing element processes a different data item in accordance with the common instruction. The data items are supplied to the processing elements independently from the instruction item. The processing elements may be divided into processing blocks. A mathematical expression evaluator (MEE) may be included.

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