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1. 发明申请

WO02065700A3 AN INTERCONNECTION SYSTEM 审中-公开
标题翻译：互连系统
公开(公告)号：WO02065700A3
公开(公告)日：2002-11-21
申请号：PCT/GB0200662
申请日：2002-02-14
申请人： CLEARSPEED TECHNOLOGY LTD , SWARBRICK IAN , WINSER PAUL , RYAN STUART
发明人： SWARBRICK IAN , WINSER PAUL , RYAN STUART
IPC分类号： G06F13/36 , G06F1/10 , G06F17/50 , H04L12/28 , H04L12/54 , H04L12/701 , H04L12/747 , H04L12/56
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： An interconnection system (110) interconnects a plurality of reusable functional units (105a), (105b), (105c). The system (110) comprises a plurality of nodes (135), (140), (145), (150), (155), (160) each node communicating with a functional unit. A plurality of data packets are transported between the functional units. Each data packet has routing information associated therewith to enable a node to direct the data packet via the interconnection system.
摘要翻译：互连系统（110）将多个可重复使用的功能单元（105a），（105b），（105c））互连。系统（110）包括与功能单元通信的多个节点（135），（140），（145），（150），（155），（160）。在功能单元之间传送多个数据分组。每个数据分组具有与其相关联的路由信息，以使节点经由互连系统引导数据分组。

2. 发明申请

WO2004045162A3 TRAFFIC MANAGEMENT ARCHITECTURE 审中-公开
标题翻译：交通管理体系结构
公开(公告)号：WO2004045162A3
公开(公告)日：2004-09-16
申请号：PCT/GB0304893
申请日：2003-11-11
申请人： CLEARSPEED TECHNOLOGY LTD , SPENCER ANTHONY
发明人： SPENCER ANTHONY
IPC分类号： H04L12/54 , H04L12/823 , H04L12/851 , H04L12/861 , H04L12/863 , H04L12/869 , H04L12/875 , H04L12/56
CPC分类号： H04L47/32 , H04L47/2441 , H04L47/50 , H04L47/562 , H04L47/60 , H04L47/6215 , H04L47/624 , H04L49/90 , H04L49/9042
摘要： An architecture for sorting incoming data packets in real time, on the fly, processes the packets and places them into an exit order queue before storing the packets. This is in contrast to the traditional way of storing first then sorting later and provides rapid processing capability. A processor (22) generates packet records from an input stream (20) and determines an exit order number for the related packet. The records are stored in an orderlist manager (24) whilst the data portions are stored in memory hub (21) for later retrieval in the exit order stored in the manager (24). The processor (22) is preferably a parallel processor array using SIMD and provided with rapid access to shared state (23) by a state engine.
摘要翻译：用于实时分类传入数据包的体系结构可以实时处理数据包，并在存储数据包之前将它们放入出口顺序队列中。这与先存储然后再排序的传统方式形成鲜明对比，并提供了快速处理能力。处理器（22）从输入流（20）产生分组记录并确定相关分组的退出顺序号。记录存储在订单列表管理器（24）中，同时数据部分存储在存储器集线器（21）中，以便随后以存储在管理器（24）中的退出顺序检索。处理器（22）优选地是使用SIMD并且由状态引擎提供对共享状态（23）的快速访问的并行处理器阵列。

3. 发明专利

GB2389689B Clock distribution system 未知
公开(公告)号：GB2389689B
公开(公告)日：2005-06-08
申请号：GB0319801
申请日：2002-02-14
申请人： CLEARSPEED TECHNOLOGY LTD , CLEARSPEED SOLUTIONS LTD , CLEARSPEED TECHNOLOGY PLC
发明人： SWARBRICK IAN , WILLIAMS DAVID
IPC分类号： G06F13/36 , G06F1/10 , G06F17/50 , H04L12/28 , H04L12/54 , H04L12/701 , H04L12/747

4. 发明专利

AU2003283539A1 DATA PACKET HANDLING IN COMPUTER OR COMMUNICATION SYSTEMS 未知
公开(公告)号：AU2003283539A1
公开(公告)日：2004-06-03
申请号：AU2003283539
申请日：2003-11-11
申请人： CLEARSPEED TECHNOLOGY LTD
发明人： CAMERON KEN , SPENCER ANTHONY
IPC分类号： H04L12/54 , H04L47/32 , H04L47/56 , H04L12/56
摘要： Variable size data packets are queued in a communication system by generating from each data packet a record portion of predetermined fixed size containing information about each packet and storing only data portions of the packets in independent memory locations in a first memory. The record portions are only stored in one or more managed queues in a second memory having fixed size memory locations equal in size to the size of the record portions. The first memory is larger than the second memory; and the memory locations in the first memory are arranged in blocks having a plurality of different sizes. The memory locations are allocated to the data portions according to the size of the data portions.

5. 发明专利

GB0324170D0 Parallel data processing systems 未知
公开(公告)号：GB0324170D0
公开(公告)日：2003-11-19
申请号：GB0324170
申请日：1999-04-09
申请人： CLEARSPEED TECHNOLOGY LTD
IPC分类号： G06F15/80

6. 发明专利

GB0319801D0 Clock distribution system 未知
公开(公告)号：GB0319801D0
公开(公告)日：2003-09-24
申请号：GB0319801
申请日：2002-02-14
申请人： CLEARSPEED TECHNOLOGY LTD
IPC分类号： G06F13/36 , G06F1/10 , G06F17/50 , H04L12/28 , H04L12/54 , H04L12/701 , H04L12/747

7. 发明专利

GB2371459A Image scaling 未知
公开(公告)号：GB2371459A
公开(公告)日：2002-07-24
申请号：GB0101410
申请日：2001-01-19
申请人： PIXELFUSION LTD , CLEARSPEED TECHNOLOGY LTD
发明人： HARASIMIUK MICHAL
IPC分类号： G06T3/40
摘要： A method and a system for scaling a digital source image consisting of a grid of X by Y pixels into a target image of a different resolution comprises the steps of/tools for: ```mapping the source pixels onto the target pixels; ```scaling the source image in the X or Y direction to produce intermediate pixels that are scaled in one direction by determining contributions to each intermediate pixel using a digital filter and accumulating the contributions for each intermediate pixel, wherein each source pixel contributes to one or more intermediate pixels and each intermediate pixel receives contributions from one or more source pixels. Scaling the intermediate pixels in the other direction by determining the contributions to each target pixel using the filter and accumulating the contributions for each target pixel wherein each intermediate pixel contributes to one or more target pixels and each target pixel receives contributions from one or more intermediate pixels. The method is preferably carried out on a Processing element (PE) array in an SIMD (Simple Instruction Multiple Data) device.

8. 发明专利

GB0203634D0 Data processing architectures 未知
公开(公告)号：GB0203634D0
公开(公告)日：2002-04-03
申请号：GB0203634
申请日：2002-02-14
申请人： CLEARSPEED TECHNOLOGY LTD
IPC分类号： G06F13/36 , G06F1/10 , G06F17/50 , H04L12/28 , H04L12/54 , H04L12/701 , H04L12/747

9. 发明专利

GB0203633D0 Method for controlling the order of datagrams 未知
公开(公告)号：GB0203633D0
公开(公告)日：2002-04-03
申请号：GB0203633
申请日：2002-02-14
申请人： CLEARSPEED TECHNOLOGY LTD
IPC分类号： G06F13/36 , G06F1/10 , G06F17/50 , H04L12/28 , H04L12/54 , H04L12/701 , H04L12/747

10. 发明专利

GB2362552A Processing graphical data 未知
公开(公告)号：GB2362552A
公开(公告)日：2001-11-21
申请号：GB0120840
申请日：2000-03-22
申请人： CLEARSPEED TECHNOLOGY LTD
发明人： CAMERON KEN , O'DEA EAMON
IPC分类号： G06T15/40 , G06T15/00
摘要： An apparatus (13) for processing graphical data includes a processing core having processor elements (15) and a controller (17). The apparatus operates to process transparent blended graphical data without the need for expensive storage and sorting routines.

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