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1. 发明申请

WO2007027414A3 MACROBLOCK NEIGHBORHOOD ADDRESS CALCULATION 审中-公开
标题翻译： MACROBLOCK NEIGHBORHOOD地址计算
公开(公告)号：WO2007027414A3
公开(公告)日：2007-07-12
申请号：PCT/US2006031480
申请日：2006-08-11
申请人： MICRONAS USA INC , SHAH ANKUR
发明人： SHAH ANKUR
IPC分类号： H04B1/66 , H04N7/12 , H04N11/02
CPC分类号： H04N19/423 , H04N19/112 , H04N19/176 , H04N19/70
摘要： Techniques for addressing syntax element information of neighboring macroblocks for processing a current macroblock based on H.264 Content Based Adaptive Binary Arithmetic Coding (CABAC) are disclosed. The techniques can be used for one line of macroblocks for Frame or Field only mode, and two lines of macroblocks for MBAFF mode. The techniques can be implemented, for example, using gate-level logic state machines as part of a system-on-chip (SOC) solution for a video/audio decoder for use in high definition television broadcasting (HDTV) applications.
摘要翻译：公开了基于H.264内容的自适应二进制算术编码（CABAC）来寻址用于处理当前宏块的相邻宏块的语法元素信息的技术。这些技术可以用于仅用于帧或场的模式的一行宏块，以及用于MBAFF模式的两行宏块。可以实现这些技术，例如，使用门级逻辑状态机作为用于高分辨率电视广播（HDTV）应用的视频/音频解码器的片上系统（SOC）解决方案的一部分。

2. 发明申请

WO2007027409A2 COMBINED ENGINE FOR VIDEO AND GRAPHICS PROCESSING 审中-公开
标题翻译：视频和图形处理组合引擎
公开(公告)号：WO2007027409A2
公开(公告)日：2007-03-08
申请号：PCT/US2006031451
申请日：2006-08-11
申请人： MICRONAS USA INC , LEE ENOCH Y , SHA LI , XIANG SHUHUA
发明人： LEE ENOCH Y , SHA LI , XIANG SHUHUA
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F3/14 , G09G5/001 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/10 , G09G2340/125 , G09G2360/06 , G09G2360/10
摘要： The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.
摘要翻译：该系统包括仲裁器，组合引擎，帧缓冲器和显示处理单元。仲裁器提供三个输入通道：用于图形的第一通道，用于视频的第二通道和用于处理器的第三通道。仲裁器在发送到系统的视频和图形以及处理器请求之间执行优先级和仲裁。仲裁器有三个输出端口连接到组合引擎。组合引擎是能够处理视频数据或图形数据的硬件引擎。组合引擎的输出被提供给帧缓冲器以存储像素数据。帧缓冲器的输出被耦合到显示处理单元，该显示处理单元渲染像素数据以进行显示。

3. 发明申请

WO2007027418A3 SYSTEMS AND METHODS FOR VIDEO TRANSFORMATION AND IN LOOP FILTERING 审中-公开
标题翻译：用于视频转换和循环滤波的系统和方法
公开(公告)号：WO2007027418A3
公开(公告)日：2007-04-26
申请号：PCT/US2006031611
申请日：2006-08-11
申请人： MICRONAS USA INC , LEE ENOCH Y
发明人： LEE ENOCH Y
IPC分类号： H04N7/04
CPC分类号： H04N19/86 , H04N19/117 , H04N19/134 , H04N19/176 , H04N19/186 , H04N19/423 , H04N19/61
摘要： The in loop filter (ILF) system comprises: an input buffer, a memory, a transform and filter unit, and an output buffer. The transform and filter unit advantageously performs video transformation and a filtering on the input data stream. The transformation is perferably performed on a macro block basis. The transform and filter unit interacts with the memory in a unique manner such that the input data required to generate an output macro block can be stored in a line buffer and a local buffer thereby minimizing the number of times the transform and filter unit accesses memory. The output buffer is also used to reorder the macro blocks, as well store processing information necessary for additional processing of the video stream. The present invention also includes novel methods for performing video transformation and in loop filtering.
摘要翻译：环路滤波器（ILF）系统包括：输入缓冲器，存储器，变换和滤波器单元以及输出缓冲器。变换和滤波器单元有利地对输入数据流进行视频变换和滤波。该转换优先以宏块为基础进行。变换和滤波器单元以独特的方式与存储器交互，使得生成输出宏块所需的输入数据可以存储在行缓冲器和本地缓冲器中，从而最小化变换和滤波器单元访问存储器的次数。输出缓冲器还用于重新排序宏块，以及对视频流的附加处理所需的存储处理信息。本发明还包括用于执行视频转换和循环滤波的新颖方法。

4. 发明申请

WO2007027418A2 SYSTEMS AND METHODS FOR VIDEO TRANSFORMATION AND IN LOOP FILTERING 审中-公开
标题翻译：用于视频变换和环路滤波的系统和方法
公开(公告)号：WO2007027418A2
公开(公告)日：2007-03-08
申请号：PCT/US2006/031611
申请日：2006-08-11
申请人： MICRONAS USA, INC. , LEE, Enoch, Y.
发明人： LEE, Enoch, Y.
IPC分类号： G06T1/00
CPC分类号： H04N19/86 , H04N19/117 , H04N19/134 , H04N19/176 , H04N19/186 , H04N19/423 , H04N19/61
摘要： The in loop filter (ILF) system comprises: an input buffer, a memory, a transform and filter unit, and an output buffer. The transform and filter unit advantageously performs video transformation and a filtering on the input data stream. The transformation is perferably performed on a macro block basis. The transform and filter unit interacts with the memory in a unique manner such that the input data required to generate an output macro block can be stored in a line buffer and a local buffer thereby minimizing the number of times the transform and filter unit accesses memory. The output buffer is also used to reorder the macro blocks, as well store processing information necessary for additional processing of the video stream. The present invention also includes novel methods for performing video transformation and in loop filtering.
摘要翻译：内环滤波器（ILF）系统包括：输入缓冲器，存储器，变换和滤波器单元以及输出缓冲器。变换和滤波器单元有利地对输入数据流执行视频变换和滤波。转换最好在宏块的基础上执行。变换和滤波器单元以独特的方式与存储器交互，使得产生输出宏块所需的输入数据可以被存储在行缓冲器和本地缓冲器中，由此最小化变换和滤波器单元访问存储器的次数。输出缓冲区也用于对宏块进行重新排序，以及存储视频流额外处理所需的处理信息。本发明还包括用于执行视频变换和环路滤波的新颖方法。

5. 发明申请

WO2007027409A3 COMBINED ENGINE FOR VIDEO AND GRAPHICS PROCESSING 审中-公开
公开(公告)号：WO2007027409A3
公开(公告)日：2007-03-08
申请号：PCT/US2006/031451
申请日：2006-08-11
申请人： MICRONAS USA, INC. , LEE, Enoch, Y. , SHA, Li , XIANG, Shuhua
发明人： LEE, Enoch, Y. , SHA, Li , XIANG, Shuhua
IPC分类号： G06T1/00
摘要： The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

6. 发明申请

WO2006119302A2 METHOD AND SYSTEM FOR SCALING, FILTERING, SCAN CONVERSION, PANORAMIC SCALING, YC ADJUSTMENT, AND COLOR CONVERSION IN A DISPLAY CONTROLLER 审中-公开
标题翻译：在显示控制器中进行缩放，过滤，扫描转换，全景缩放，YC调整和颜色转换的方法和系统
公开(公告)号：WO2006119302A2
公开(公告)日：2006-11-09
申请号：PCT/US2006016862
申请日：2006-05-02
申请人： MICRONAS USA INC , TIAN YU T , HUANG QIFAN , SHA LI
发明人： TIAN YU T , HUANG QIFAN , SHA LI
IPC分类号： G09G5/00 , G06F17/10 , G06T3/40 , G09G5/391 , H04N5/44 , H04N9/64 , H04N11/20
CPC分类号： H04N11/20 , G06T3/4007 , G06T3/4038 , G09G5/391 , G09G2340/0407 , H04N7/01 , H04N7/0122 , H04N7/0125 , H04N9/64 , H04N9/641 , H04N9/67 , H04N9/68
摘要： Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations.
摘要翻译：公开了用于执行全景缩放的技术，其减少全景图像中的可见失真。此外，公开了用于执行组合YC调整和颜色转换的技术，通过减少当将YC调整和颜色转换实现为单独操作时所需的逻辑门数和存储缓冲器的数量来减小视频操纵硬件的尺寸和功率要求。

7. 发明申请

WO2007027409A8 COMBINED ENGINE FOR VIDEO AND GRAPHICS PROCESSING 审中-公开
公开(公告)号：WO2007027409A8
公开(公告)日：2007-12-27
申请号：PCT/US2006031451
申请日：2006-08-11
申请人： MICRONAS USA INC , LEE ENOCH Y , SHA LI , XIANG SHUHUA
发明人： LEE ENOCH Y , SHA LI , XIANG SHUHUA
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F3/14 , G09G5/001 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/10 , G09G2340/125 , G09G2360/06 , G09G2360/10
摘要： The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

8. 发明申请

WO2007027402A2 MULTI-STAGE CABAC DECODING PIPELINE 审中-公开
标题翻译：多级CABAC解码管道
公开(公告)号：WO2007027402A2
公开(公告)日：2007-03-08
申请号：PCT/US2006/031353
申请日：2006-08-11
申请人： MICRONAS USA, INC. , SHAH, Ankur , PENG, Liang
发明人： SHAH, Ankur , PENG, Liang
IPC分类号： G06T1/00
CPC分类号： H04N19/436 , H04N19/13 , H04N19/44 , H04N19/61
摘要： An architecture capable of Content Based Adaptive Binary Arithmetic Coding (CABAC) decoding at the syntax element level is disclosed. The architecture employs a multi-stage stage pipeline to implement the functions of CABAC bit parsing and decoding processes based on the H.264 CABAC algorithm. Each stage can be carried out in one clock cycle, and not all stages are executed for every bit (e.g., average of 4 cycle per bit, or 30 frames per second). The architecture can be implemented, for example, using gate-level logic state machines as part of a system-on-chip (SOC) solution for a video/audio decoder for use in high definition television broadcasting (HDTV) applications. Other such video/audio decoder applications are enabled as well.
摘要翻译：公开了一种能够在语法元素级别进行基于内容的自适应二进制算术编码（CABAC）解码的架构。该架构采用多阶段流水线实现基于H.264 CABAC算法的CABAC位解析和解码过程的功能。每个级可以在一个时钟周期内执行，并不是每个位都执行所有级（例如，每位4个周期的平均值，或每秒30个帧）。该架构可以实现，例如，使用门级逻辑状态机作为用于高分辨率电视广播（HDTV）应用的视频/音频解码器的片上系统（SOC）解决方案的一部分。其他这样的视频/音频解码器应用也被启用。

9. 发明申请

WO2006119302A3 SYSTEM FOR SCALING, YC ADJUSTMENT, AND COLOR CONVERSION IN A DISPLAY CONTROLLER 审中-公开
公开(公告)号：WO2006119302A3
公开(公告)日：2006-11-09
申请号：PCT/US2006/016862
申请日：2006-05-02
申请人： MICRONAS USA, INC. , TIAN, Yu, T. , HUANG, Qifan , SHA, Li
发明人： TIAN, Yu, T. , HUANG, Qifan , SHA, Li
IPC分类号： H04N1/393 , H04N7/01 , H04N11/20
摘要： Techniques for performing panoramic scaling (224) are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion (226) are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion (226) are implemented as separate operations.

10. 发明申请

WO2007027402A3 MULTI-STAGE CABAC DECODING PIPELINE 审中-公开
标题翻译：多级CABAC解码管道
公开(公告)号：WO2007027402A3
公开(公告)日：2007-07-12
申请号：PCT/US2006031353
申请日：2006-08-11
申请人： MICRONAS USA INC , SHAH ANKUR , PENG LIANG
发明人： SHAH ANKUR , PENG LIANG
IPC分类号： G06T1/00
CPC分类号： H04N19/436 , H04N19/13 , H04N19/44 , H04N19/61
摘要： An architecture capable of Content Based Adaptive Binary Arithmetic Coding (CABAC) decoding at the syntax element level is disclosed. The architecture employs a multi-stage stage pipeline to implement the functions of CABAC bit parsing and decoding processes based on the H.264 CABAC algorithm. Each stage can be carried out in one clock cycle, and not all stages are executed for every bit (e.g., average of 4 cycle per bit, or 30 frames per second). The architecture can be implemented, for example, using gate-level logic state machines as part of a system-on-chip (SOC) solution for a video/audio decoder for use in high definition television broadcasting (HDTV) applications. Other such video/audio decoder applications are enabled as well.
摘要翻译：公开了一种能够在语法元素级进行基于内容的自适应二进制算术编码（CABAC）解码的体系结构。该架构采用多级阶段流水线来实现基于H.264 CABAC算法的CABAC位解析和解码过程的功能。每个阶段可以在一个时钟周期内执行，并且并非每个阶段都执行所有阶段（例如，每个比特的平均4个周期或每秒30个帧）。例如，可以使用门级逻辑状态机作为用于高清晰度电视广播（HDTV）应用中的视频/音频解码器的片上系统（SOC）解决方案的一部分来实现该架构。其他这样的视频/音频解码器应用也被启用。

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