专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07401319B2 Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design 有权
标题翻译：集成电路布图设计中代表性和计算复用的光罩级层次管理方法与系统
公开(公告)号：US07401319B2
公开(公告)日：2008-07-15
申请号：US11021783
申请日：2004-12-23
申请人： Chi-Song Horng , Devendra Joshi , Anwei Liu
发明人： Chi-Song Horng , Devendra Joshi , Anwei Liu
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.
摘要翻译：分层表示使用单元定义（CellDef）的概念来封装子电路的详细内部组成。 CellDef作为操作重用的自然单元。如果基于CellDef或一个单元实例的分析或操作所需的计算（例如寄生提取，RET，设计规则确认（DRC）或OPC））可以无需或最小的额外努力应用于所有或重要的单元的其他实例的子集可以实现计算量的非常大的减少。此外，分层表示还允许将整个分析/操作任务划分成子任务的集合，例如子集。每个CellDef一个。然后可以将多个作业分布在网络上的大量计算节点上以用于并发执行。虽然这可能不会减少总体计算时间，但总体周转时间（TAT）的大幅减少本身就是非常有益的。

2. 发明授权

US07224437B2 Method for measuring and verifying stepper illumination 有权
标题翻译：步进照明的测量和验证方法
公开(公告)号：US07224437B2
公开(公告)日：2007-05-29
申请号：US11141803
申请日：2005-05-31
申请人： Gökhan Perçin , Abdurrahman Sezginer , Franz Xaver Zach
发明人： Gökhan Perçin , Abdurrahman Sezginer , Franz Xaver Zach
IPC分类号： G03B27/42 , G03B27/52
CPC分类号： G03F7/7025 , G03F7/70591
摘要： An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.
摘要翻译：用于表征曝光工具的照明光瞳的装置和方法包括在多个测试位置处形成多个针孔测试图案，以便于定位测试图案边缘以从其中提取曝光工具的照明光瞳特性。

3. 发明申请

US20060248495A1 Method and apparatus of model-based photomask synthesis 有权
公开(公告)号：US20060248495A1
公开(公告)日：2006-11-02
申请号：US11203505
申请日：2005-08-13
申请人： Abdurrahman Sezginer
发明人： Abdurrahman Sezginer
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： An apparatus and method for improving image quality in a photolithographic process includes calculating a figure-of-demerit for a photolithographic mask function and then adjusting said photolithographic mask function to reduce the figure of demerit.

4. 发明申请

US20050273753A1 Method and system for designing manufacturable patterns that account for the pattern- and position-dependent nature of patterning processes 有权
标题翻译：用于设计可制造图案的方法和系统，其描述了图案化工艺的图案和位置依赖性质
公开(公告)号：US20050273753A1
公开(公告)日：2005-12-08
申请号：US10861170
申请日：2004-06-04
申请人： Abdurrahman Sezginer
发明人： Abdurrahman Sezginer
IPC分类号： G03F7/20 , G06F17/50 , G21K5/10
CPC分类号： G03F7/70433 , G03F7/70425 , G03F7/705 , G06F17/50 , G06F2217/12 , Y02P90/265
摘要： Computational models of a patterning process are described. Any one of these computational models can be implemented as computer-readable program code embodied in computer-readable media. The embodiments described herein explain techniques that can be used to adjust parameters of these models according to measurements, as well as how predictions made from these models can be used to correct lithography data. Corrected lithography data can be used to manufacture a device, such as an integrated circuit.
摘要翻译：描述了图案化过程的计算模型。这些计算模型中的任何一个可以被实现为体现在计算机可读介质中的计算机可读程序代码。这里描述的实施例解释了可以用于根据测量来调整这些模型的参数的技术，以及如何使用这些模型做出的预测来校正光刻数据。校正的光刻数据可用于制造诸如集成电路的器件。

5. 发明申请

US20110154281A1 OPTICAL LITHOGRAPHY CORRECTION PROCESS 有权
标题翻译：光学光刻校正过程
公开(公告)号：US20110154281A1
公开(公告)日：2011-06-23
申请号：US12971845
申请日：2010-12-17
申请人： Franz Xaver Zach
发明人： Franz Xaver Zach
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G06F2217/12 , Y02P90/265 , Y10S977/834
摘要： A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.
摘要翻译：用于校正过程关键布局的装置和方法包括表征一组最坏情况处理变化中的各个对模拟纳米电路布局设计的影响，然后基于这种表征来校正模拟纳米电路布局中的布局几何形状。

6. 发明授权

US07392502B2 Method for real time monitoring and verifying optical proximity correction model and method 有权
标题翻译：用于实时监测和验证光学邻近校正模型和方法的方法
公开(公告)号：US07392502B2
公开(公告)日：2008-06-24
申请号：US11169616
申请日：2005-06-30
申请人： Gökhan Percin , Ram Ramanujam , Franz Xaver Zach , Koichi Suzuki
发明人： Gökhan Percin , Ram Ramanujam , Franz Xaver Zach , Koichi Suzuki
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F1/36 , G03F1/44 , G03F7/70441 , G03F7/70683
摘要： This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.
摘要翻译：本发明涉及一种用于实时监测和验证生产中的光学邻近校正（OPC）模型和方法的方法。在对集成电路布局进行OPC之前，应准确准确地描述涉及光刻的光学，物理和化学过程的模型。通常，使用通过相同的光刻，图案化和蚀刻工艺运行晶片获得的测量来校准模型。在本发明中，提出了一种用于在生产或监控晶圆上验证和监测校准模型的新型实时方法：将光学邻近校正（OPC-ed）测试和验证结构放置在生产或监视器的划线或切割线上晶圆，并且具有预定的时间表，这些测试和验证结构的关键尺寸和图像在晶片和曝光场之间进行监控。

7. 发明授权

US07318214B1 System and method for reducing patterning variability in integrated circuit manufacturing through mask layout corrections 有权
标题翻译：通过掩模布局校正减少集成电路制造中的图形变化的系统和方法
公开(公告)号：US07318214B1
公开(公告)日：2008-01-08
申请号：US10841079
申请日：2004-05-07
申请人： Roy V. Prasad , Chi-Song Horng , Ram S. Ramanujam
发明人： Roy V. Prasad , Chi-Song Horng , Ram S. Ramanujam
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F1/68 , G03F1/70 , G03F1/76
摘要： The present invention provides a system and method of modifying the mask layout shapes of an integrated circuit layout design to compensate for reticle field location-specific systematic CD variations resulting from mask writing process variations, lens imperfections in lithographic patterning, and photoresist process variations. Called PLC (Process-optimized Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular mask-writer-patterning-tools-and-resist-process combination, and are performed on a reticle-wide basis. Furthermore, for each geometric shape in the mask layout, the amount of modification is determined based on a categorization of the type of the shape, the specific location in the reticle field the particular shape falls in, its context (i.e., surrounding patterns, orientation, etc.), as well as certain photoresist parameters to be used in the patterning process.
摘要翻译：本发明提供了一种修改集成电路布局设计的掩模布局形状的系统和方法，以补偿由掩模写入过程变化，平版印刷图案中的晶体缺陷和光致抗蚀剂工艺变化导致的标线片位置特定系统CD变化。被称为PLC（过程优化布局补偿），根据本发明的每组补偿规则是针对特定的掩模 - 写入器 - 图案形成 - 工具和 - 抗蚀剂 - 处理组合而专门设计的，并且在掩模版宽度的基础上执行。此外，对于掩模布局中的每个几何形状，修改量基于形状的类型的分类，特定形状所在的标线场中的特定位置，其上下文（即，周围图案，取向等），以及在图案化工艺中使用的某些光刻胶参数。

8. 发明申请

US20060251994A1 Apparatus and method for characterizing an image system in lithography projection tool 有权
标题翻译：用于表征光刻投影工具中的图像系统的装置和方法
公开(公告)号：US20060251994A1
公开(公告)日：2006-11-09
申请号：US11203331
申请日：2005-08-13
申请人： Hsu-Ting Huang , Abdurrahman Sezginer
发明人： Hsu-Ting Huang , Abdurrahman Sezginer
IPC分类号： G03C5/00
CPC分类号： G03F7/706
摘要： A system and method for characterizing an imaging system causes a diffraction image indicative of a test structure having a generalized line-grating to be formed and then extracts from a measurement of the diffraction image a lens transmittance function, a photoresist property or a defocus distance.
摘要翻译：用于表征成像系统的系统和方法使得将形成指示具有广义线光栅的测试结构的衍射图像，然后从衍射图像的测量中提取透镜透射函数，光致抗蚀剂性质或散焦距离。

9. 发明申请

US20060248499A1 Apparatus and method for breaking up and merging polygons 有权
公开(公告)号：US20060248499A1
公开(公告)日：2006-11-02
申请号：US11203522
申请日：2005-08-13
申请人： Abdurrahman Sezginer , Roy Prasad
发明人： Abdurrahman Sezginer , Roy Prasad
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G03F7/70291 , G03F7/70441
摘要： A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in the figure-of-demerit, wherein disrupting polygons includes any of the following polygon disruptions: breaking up, merging, or deleting polygons.

10. 发明申请

US20060075379A1 Method and system for managing design corrections for optical and process effects based on feature tolerances 有权
标题翻译：基于特征公差管理光学和过程效果的设计校正的方法和系统
公开(公告)号：US20060075379A1
公开(公告)日：2006-04-06
申请号：US10955527
申请日：2004-09-30
申请人： Vishnu Kamat
发明人： Vishnu Kamat
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and/or processing effects for example photoresist response and etching effects. The method comprises determining a correction for the repeating pattern based on a first set of tolerances for features of the repeating pattern. Then, the suitability of the corrections is evaluated for instances of the repeating pattern in the integrated circuit design based on a second set of tolerances, which is different from the first set of tolerances. This can be used to preserve much of the hierarchy of the layout data in the corrected, or lithography, data. This can be achieved during the OPC process, thus avoiding the post OPC compaction. It can further take advantage of the fact that, for a given physical layer of a chip for example, different portions of the representing design polygons typically have different requirements on pattern fidelity on the wafer while perturbations may vary as a function of field position. By applying knowledge of the feature tolerances, and allowing design corrections only when tolerances are not met, the data explosion that occurs when moving from layout to lithography data can be contained without sacrificing accuracy.
摘要翻译：描述了在集成电路设计中修改重复图案的实例以校正渲染期间的扰动的方法。在典型的实施例中，这些校正是在掩模图案投影到晶片上和/或处理效果例如光致抗蚀剂响应和蚀刻效果时校正光学效果的光学邻近校正。该方法包括基于重复图案的特征的第一组公差来确定针对重复图案的校正。然后，基于与第一组公差不同的第二组公差，对集成电路设计中的重复图案的实例进行校正的适用性。这可以用于保留校正或光刻数据中布局数据的大部分层次。这可以在OPC过程中实现，从而避免后OPC压缩。可以进一步利用以下事实：对于给定的芯片的物理层，例如，表示设计多边形的不同部分通常对晶片上的图案保真度具有不同的要求，同时扰动可以随现场位置的函数而变化。通过应用特征公差的知识，并且只有在不满足公差的情况下才能进行设计校正，可以在不牺牲精度的情况下包含从布局移动到光刻数据时发生的数据爆炸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式