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    • 2. 发明申请
    • Native high-voltage n-channel LDMOSFET in standard logic CMOS
    • 标准逻辑CMOS中的原生高压n沟道LDMOSFET
    • US20060001087A1
    • 2006-01-05
    • US10884236
    • 2004-07-02
    • Bin Wang
    • Bin Wang
    • H01L29/76
    • H01L29/4983H01L29/4916H01L29/7835
    • A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain terminal coupled to the second n+ doped region, a p+ doped region disposed in the substrate, a body terminal coupled to the p+ doped region, a dielectric layer disposed over the p− doped substrate and a portion of the n− well, a first trench disposed in the n− well, the trench filled with a dielectric material that is in contact with the dielectric layer, a second trench disposed at least partially in the n− well, the second trench filled with a dielectric material and isolating the second n+ region from the p+ region, and a gate partially or fully reversely doped with p+ implant (or an equivalent technique) and disposed over the dielectric layer and a portion of the first trench.
    • 原生高压n沟道LDMOSFET包括p掺杂衬底,设置在p掺杂衬底中的第一n +掺杂区,耦合到第一n +掺杂区的源极,设置在衬底中的n阱, 设置在n阱中的第二n +掺杂区域,耦合到第二n +掺杂区域的漏极端子,设置在衬底中的p +掺杂区域,耦合到p +掺杂区域的主体端子,设置在p掺杂区域上的介电层 衬底和n阱的一部分,设置在n阱中的第一沟槽,填充有与介电层接触的电介质材料的沟槽,至少部分地设置在n阱中的第二沟槽, 填充有电介质材料并且将第二n +区域与p +区域隔离的第二沟槽和部分地或完全地反向掺杂有p +注入(或等效技术)并且设置在电介质层和第一沟槽的一部分上的栅极。
    • 3. 发明申请
    • RFID readers transmitting preambles denoting data rate and methods
    • RFID阅读器传输前缀,表示数据速率和方法
    • US20050237162A1
    • 2005-10-27
    • US10890662
    • 2004-07-13
    • John HydeChristopher Diorio
    • John HydeChristopher Diorio
    • G06K7/00H04Q5/22
    • G06K7/0008G06K7/10297
    • RFID readers transmit data to query tags at one or more data rates. Before transmitting data, the RFID readers also transmit special preambles that inform of the data rate that will be used for transmitting the data. The preambles have a call aspect and a rate aspect. The rate aspect has a feature substantially determined from a rate selected for transmitting the data. The feature may encode the rate indirectly or explicitly. The call aspect may be implemented by call transitions that define a timing, whose duration is independent of the selected rate. The duration may be advantageously set according to an assumed state of the RFID tag bandwidth filter. Therefore an RFID tag may use the call aspect of the preamble to prepare itself for receiving data, and the rate aspect to determine its rate of transmission for setting its filter bandwidth accordingly.
    • RFID读取器以一个或多个数据速率将数据传输到查询标签。 在发送数据之前,RFID阅读器还传送特定的前导码,通知将用于传输数据的数据速率。 前导码具有呼叫方面和速率方面。 速率方面具有从选择用于发送数据的速率基本上确定的特征。 该特征可以间接地或明确地编码速率。 呼叫方面可以通过定义定时的呼叫转换来实现,其持续时间与所选择的速率无关。 可以根据RFID标签带宽滤波器的假定状态有利地设置持续时间。 因此,RFID标签可以使用前导码的呼叫方面来准备其接收数据,并且速率方面用于确定其传输速率以相应地设置其滤波器带宽。
    • 4. 发明申请
    • Graded-junction high-voltage MOSFET in standard logic CMOS
    • 分级结高压MOSFET在标准逻辑CMOS
    • US20050236666A1
    • 2005-10-27
    • US10884326
    • 2004-07-02
    • Bin Wang
    • Bin Wang
    • H01L29/06H01L29/10H01L29/423H01L29/76H01L29/78
    • H01L29/7835H01L29/0653H01L29/1045H01L29/42368
    • A high-voltage graded junction LDMOSFET includes a substrate of a first conductivity type, a well of the first conductivity type disposed in the substrate, a first region of a second conductivity type disposed in the well of the first conductivity type, a source terminal coupled to the first region of the second conductivity type, a well of the second conductivity type disposed in the substrate, a second region of the second conductivity type disposed in the well of the second conductivity type, a drain terminal coupled to the second region of the second conductivity type, a region of the first conductivity type disposed in the substrate, a body terminal coupled to the region of the first conductivity type, a graded-junction region formed of material of the first conductivity type separating the well of the first conductivity type and the well of the second conductivity type, the material of the first conductivity type in the graded-junction region doped at least an order of magnitude less than the wells, a dielectric layer disposed over the well of the first conductivity type, the graded-junction region and a portion of the well of the second conductivity type, a first isolator disposed in the well of the second conductivity type, the isolator including a dielectric material that is in contact with the dielectric layer, a second isolator disposed at least partially in the well of the second conductivity type, the second isolator including a dielectric material and isolating the second region of the second conductivity type from the region of the first conductivity type, and a gate disposed over the dielectric layer and a portion of the first isolator.
    • 高压梯度结LDMOSFET包括第一导电类型的衬底,设置在衬底中的第一导电类型的阱,设置在第一导电类型的阱中的第二导电类型的第一区域,源极端子耦合 到第二导电类型的第一区域,设置在基板中的第二导电类型的阱,设置在第二导电类型的阱中的第二导电类型的第二区域,耦合到第二导电类型的第二区域的漏极端子 第二导电类型,设置在基板中的第一导电类型的区域,耦合到第一导电类型的区域的主体端子,由第一导电类型的材料形成的分级接合区域,该第一导电类型的材料将第一导电类型的阱 和第二导电类型的阱,掺杂了至少一个数量级的渐变结区域中的第一导电类型的材料 小于所述阱的介质层,设置在所述第一导电类型的阱中的介电层,所述渐变接合区域和所述第二导电类型的阱的一部分,设置在所述第二导电类型的阱中的第一隔离器,所述隔离器 包括与电介质层接触的电介质材料,至少部分地设置在第二导电类型的阱中的第二隔离器,第二隔离器包括电介质材料,并将第二导电类型的第二区域与 第一导电类型和设置在电介质层上的栅极和第一隔离器的一部分。
    • 7. 发明申请
    • PFET nonvolatile memory
    • PFET非易失性存储器
    • US20050063235A1
    • 2005-03-24
    • US10839985
    • 2004-05-05
    • Alberto PesaventoFrederic BernardJohn Hyde
    • Alberto PesaventoFrederic BernardJohn Hyde
    • G11C16/04G11C20060101G11C5/00G11C7/06G11C11/34G11C16/02G11C16/06G11C16/28H01L21/8247H01L27/115H01L29/788H01L29/792
    • G11C16/0441G11C16/28G11C2216/10H01L27/115H01L29/7883
    • A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage which can be used to represent information such as binary bits. A control capacitor structure having its first terminal coupled to a first voltage source and its second terminal coupled to the floating gate and a tunneling capacitor structure having its first terminal coupled to a second voltage source and its second terminal coupled to the floating gate are utilized in each embodiment. The control capacitor structure is fabricated so that it has much more capacitance than does the tunneling capacitor structure (and assorted stray capacitance between the floating gate and various other nodes of the cell). Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the floating gate, thus controlling the charge on the floating gate and the information value stored thereon.
    • 使用其源极连接到电源(Vdd)的浮栅pFET读出晶体管构造非易失性存储单元,其漏极提供可被感测以确定单元的状态的电流。 pFET读出晶体管的栅极提供电荷存储,可用于表示诸如二进制位之类的信息。 一种控制电容器结构,其第一端耦合到第一电压源,其第二端耦合到浮置栅极,并且隧道电容器结构具有耦合到第二电压源的第一端和其耦合到浮置栅极的第二端。 各实施例。 制造控制电容器结构使得其具有比隧道电容器结构(以及浮动栅极和电池的各种其他节点之间的杂散电容)多得多的电容。 对施加到第一电压源和第二电压源(和Vdd)的电压的操纵控制电容器结构和pFET电介质两端的电场,从而使Fowler-Nordheim将电子隧穿到浮栅上和从浮栅上,从而控制电荷 浮动门和存储在其上的信息值。