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1. 发明申请

US20160042206A1 POWERING RFID TAGS USING MULTIPLE SYNTHESIZED-BEAM RFID READERS 有权
标题翻译：使用多个合成光束RFID读取器为RFID标签提供动力
公开(公告)号：US20160042206A1
公开(公告)日：2016-02-11
申请号：US14388793
申请日：2014-03-13
申请人： Alberto Pesavento , Christopher Diorio
发明人： Alberto Pesavento , Christopher Diorio
IPC分类号： G06K7/10
CPC分类号： G06K7/10158 , G06K7/10178 , G06K7/10297 , G06Q10/087 , H01Q1/2216 , H01Q3/26 , H01Q21/061
摘要： Synthesized-beam RFID readers may be used to manage and provide information about RFID tag populations. In one embodiment, two or more synthesized-beam readers synthesize respective RF beams towards a tag location. The synthesized-beam readers may coordinate their pointing by means of a controller, a peer-to-peer network, or by using a master-slave arrangement. The synthesized-beam readers may coordinate their transmissions to increase the RF energy available to a tag at the pointing location.
摘要翻译：合成光束RFID读取器可用于管理和提供关于RFID标签种群的信息。在一个实施例中，两个或多个合成束读取器将相应的RF波束合成到标签位置。合成光束读取器可以通过控制器，对等网络或通过使用主 - 从装置来协调它们的指向。合成光束读取器可以协调它们的传输以增加在指向位置处的标签可用的RF能量。

2. 发明授权

US08416630B2 PFET nonvolatile memory 有权
标题翻译： PFET非易失性存储器
公开(公告)号：US08416630B2
公开(公告)日：2013-04-09
申请号：US13342834
申请日：2012-01-03
申请人： Alberto Pesavento , John D. Hyde
发明人： Alberto Pesavento , John D. Hyde
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C11/005 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/3427 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2216/10 , G11C2216/26
摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.
摘要翻译：使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim隧穿电子在浮栅上和离开浮栅，控制浮栅上的电荷和信息存储在其上。

3. 发明授权

US07733227B1 RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action 有权
标题翻译： RFID标签电路和用于感测自身电力的方法，以预先确定所请求动作的可行性
公开(公告)号：US07733227B1
公开(公告)日：2010-06-08
申请号：US11624197
申请日：2007-01-17
申请人： Alberto Pesavento , Vadim Gutnik , John D. Hyde
发明人： Alberto Pesavento , Vadim Gutnik , John D. Hyde
IPC分类号： G08B13/14
CPC分类号： G06K7/0008 , G06K19/0707 , G06K19/0712 , G06K19/07749
摘要： Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.
摘要翻译：基于可用的标签功率电平，RFID标签中预先确定读取器所请求的动作的可行性。执行被设计为消耗人为高电平的预测试，并且监视功率电平以确定是否满足预设条件。预测试可以包括激活所选择的组件，例如存储器和相关联的支持电路。如果不满足预设条件，请求的操作将中止，并将错误消息传送给读卡器。

4. 发明授权

US07388420B2 Rewriteable electronic fuses 有权
标题翻译：可重写电子保险丝
公开(公告)号：US07388420B2
公开(公告)日：2008-06-17
申请号：US10814866
申请日：2004-03-30
申请人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
发明人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
IPC分类号： H01H37/76
CPC分类号： G11C16/0441 , G11C7/20 , G11C14/00 , G11C16/045
摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.
摘要翻译：可重写电子熔丝包括耦合到一个或多个非易失性存储元件的锁存器和/或逻辑门。非易失性存储器元件被配置为被编程为能够使相关联的电子电路稳定到预定状态的存储器值，因为上电或复位信号被施加到保险丝。虽然不是必需的，但是在可重写电子熔丝中使用的非易失性存储元件可以包括浮栅晶体管。存储在给定浮栅晶体管的浮置栅极上的电荷量确定存储器值，并且因此确定保险丝上电或复位时保险丝熔断的状态。

5. 发明授权

US07283390B2 Hybrid non-volatile memory 有权
标题翻译：混合非易失性存储器
公开(公告)号：US07283390B2
公开(公告)日：2007-10-16
申请号：US11237099
申请日：2005-09-28
申请人： Alberto Pesavento
发明人： Alberto Pesavento
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C11/005 , G11C16/0416 , G11C16/0441 , G11C16/3477 , G11C16/3486 , G11C2216/10 , G11C2216/26
摘要： A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.
摘要翻译：非易失性存储器（NVM）电路包括共享公共支持电路的至少两种类型的NVM子电路。不同类型的NVM子电路包括在寻址时提供逻辑输出的普通NVM电路，在转换到通电状态时提供输出的可编程熔丝，提供ON / OFF状态输出的NVM电路等。一些输出用于在上电之后校准器件内的电路。其他输出用于存储由各种电路采用的信息。

6. 发明授权

US07242614B2 Rewriteable electronic fuses 有权
公开(公告)号：US07242614B2
公开(公告)日：2007-07-10
申请号：US10813907
申请日：2004-03-30
申请人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
发明人： Christopher J. Diorio , Frédéric J. Bernard , Todd E. Humes , Alberto Pesavento
IPC分类号： G11C11/34 , G11C17/18
CPC分类号： G11C16/0441 , G11C14/00 , G11C16/045 , H01L27/105 , H01L27/115 , H01L29/7883 , H03K3/02335
摘要： Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

7. 发明申请

US20060071793A1 RFID tag using hybrid non-volatile memory 有权
标题翻译：使用混合非易失性存储器的RFID标签
公开(公告)号：US20060071793A1
公开(公告)日：2006-04-06
申请号：US11237012
申请日：2005-09-28
申请人： Alberto Pesavento
发明人： Alberto Pesavento
IPC分类号： G08B13/14
CPC分类号： G06K19/0723
摘要： An RFID tag includes a non-volatile memory (NVM) circuit with at least two distinct types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.
摘要翻译： RFID标签包括具有共享公共支持电路的至少两种不同类型的NVM子电路的非易失性存储器（NVM）电路。不同类型的NVM子电路包括在寻址时提供逻辑输出的普通NVM电路，在转换到通电状态时提供输出的可编程熔丝，提供ON / OFF状态输出的NVM电路等。一些输出用于在上电之后校准器件内的电路。其他输出用于存储由各种电路采用的信息。

8. 发明申请

US20050052201A1 High-voltage switches in single-well CMOS processes 有权
标题翻译：单井CMOS工艺中的高压开关
公开(公告)号：US20050052201A1
公开(公告)日：2005-03-10
申请号：US10814867
申请日：2004-03-30
申请人： Frederic Bernard , Christopher Diorio , Troy Gilliland , Alberto Pesavento , Kaila Raby , Terry Hass , John Hyde
发明人： Frederic Bernard , Christopher Diorio , Troy Gilliland , Alberto Pesavento , Kaila Raby , Terry Hass , John Hyde
IPC分类号： H03K3/356 , H03K17/10 , H03K19/0175
CPC分类号： H03K3/356113 , H03K17/102
摘要： Circuits are provided for high-voltage switching in single-well CMOS processes.
摘要翻译：电路用于单井CMOS工艺中的高压开关。

9. 发明授权

US06853583B2 Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells 有权
标题翻译：用于防止基于pFET的非易失性存储单元中的过度隧穿的方法和装置
公开(公告)号：US06853583B2
公开(公告)日：2005-02-08
申请号：US10245183
申请日：2002-09-16
申请人： Christopher J. Diorio , Chad Lindhorst , Shail Srinivas , Alberto Pesavento , Troy Gilliland
发明人： Christopher J. Diorio , Chad Lindhorst , Shail Srinivas , Alberto Pesavento , Troy Gilliland
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3477 , G11C16/3404 , G11C16/3468 , G11C16/3472
摘要： Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.
摘要翻译：方法和装置可以防止基于pFET的非易失性浮动栅极存储器（NVM）单元中的超导。在其中从基于pFET的NVM单元的浮置栅极去除电荷载流子的隧穿过程中，监测存储单元晶体管的沟道电流，并将其与在注入中维持导通通道所需的预定最小沟道电流进行比较晶体管的存储单元。当监测的通道电流下降到预定的最小通道电流以下时，电荷载流子通过冲击电离热电子注入（IHEI）注入到浮动栅极上，从而避免了超导。

10. 发明申请

US20120099380A1 PFET Nonvolatile Memory 有权
标题翻译： PFET非易失性存储器
公开(公告)号：US20120099380A1
公开(公告)日：2012-04-26
申请号：US13342834
申请日：2012-01-03
申请人： Alberto Pesavento , John D. Hyde
发明人： Alberto Pesavento , John D. Hyde
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0433 , G11C11/005 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/3427 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2216/10 , G11C2216/26
摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.
摘要翻译：使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim在浮栅上和从浮栅上隧穿隧道，控制浮栅上的电荷和信息存储在其上。

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