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1. 发明申请

WO1996031031A1 HIGH SPEED SYNCHRONOUS DIGITAL DATA BUS SYSTEM HAVING UNTERMINATED DATA AND CLOCK BUSES 审中-公开
标题翻译：具有不完整数据和时钟总线的高速同步数字总线系统
公开(公告)号：WO1996031031A1
公开(公告)日：1996-10-03
申请号：PCT/US1996004087
申请日：1996-03-26
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , REYMOND, Welles
IPC分类号： H04L07/00
CPC分类号： G06F1/10 , G06F13/4072 , H03L7/0812 , H04L7/0008 , H04L2007/047
摘要： A high speed synchronous digital bidirectional data bus system (10) is provided and includes an M-bit unterminated data bus (14), an unterminated standing sine wave clock bus (12) and a plurality of integrated circuit bus interfaces (16a...). Each IC bus interface (16a...) is preferably substantially incorporated on a single CMOS LSI chip and includes M bus drivers with associated receive data logic, M data receivers with associated receive data logic, and a clock receiver (19). The output currents of the bus drivers (30) on all of the chips are preferably stabilized so that each driver drives the bus (14) at substantially the same output current. The drivers are preferably complementary polar driven CMOS logic elements. For this case, for each data receiver (20a-20h), a bus keeper (44) is coupled to the output and the input of the bus receiver to maintain the last state of the data bus. In addition, the clock receivers (19) and the data receivers (20a-20h) are embodied as high speed comparators (22) having internal hysteresis. The clock receivers (19) are preferably provided with a delay generator with produces a "guard band" during which the bus drivers (30) are tri-stated before they can drive the data bus. This prevents conflicts on the bus and guarantees end sampling of data.
摘要翻译：提供了一种高速同步数字双向数据总线系统（10），包括一个M位未终止的数据总线（14），一个未终端的正弦波时钟总线（12）和多个集成电路总线接口（16a ...））。每个IC总线接口（16a ...）优选地基本上并入在单个CMOS LSI芯片上，并且包括具有相关联的接收数据逻辑的M总线驱动器，具有相关联的接收数据逻辑的M个数据接收器和时钟接收器（19）。所有芯片上的总线驱动器（30）的输出电流优选地是稳定的，使得每个驱动器以基本上相同的输出电流驱动总线（14）。驱动器优选地是互补极性驱动的CMOS逻辑元件。对于这种情况，对于每个数据接收器（20a-20h），总线保持器（44）耦合到总线接收器的输出和输入端以保持数据总线的最后状态。此外，时钟接收器（19）和数据接收器（20a-20h）被实现为具有内部滞后的高速比较器（22）。时钟接收器（19）优选地设置有延迟发生器，其产生“保护带”，在该保护带期间，总线驱动器（30）在它们可以驱动数据总线之前是三态的。这可以防止总线上的冲突，并保证数据的最终采样。

2. 发明申请

WO1992020203A1 INTEGRATED CIRCUIT PACKAGES USING TAPERED SPRING CONTACT LEADS FOR DIRECT MOUNTING TO CIRCUIT BOARDS 审中-公开
标题翻译：集成电路组件使用旋转式弹簧触点引线直接安装到电路板上
公开(公告)号：WO1992020203A1
公开(公告)日：1992-11-12
申请号：PCT/US1992003847
申请日：1992-05-08
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , REYMOND, Welles, K.
IPC分类号： H05K01/00
CPC分类号： H01R4/5016 , H01L23/49555 , H01L2924/0002 , H01R4/48 , H01R12/52 , H01R12/58 , H01R12/712 , H05K3/325 , H05K2201/10393 , H05K2203/176 , H01L2924/00
摘要： An integrated circuit package (10) is provided with a plurality of contact element leads (91), each lead having a first portion for making electrical connection with the integrated circuit (130) and a second tapered contact portion for mating with a conductive rim of the hole of a circuit board. In conjunction with the integrated circuit package (10), a fastener (150) is provided for holding the tapered contact elements (91) in mating relationship with the conductive rims. The tapered contact portion of the lead of the integrated circuit package may take any of various forms, as long as the lead is tapered and resilient so that proper mating with a conductive rim can be accomplished. Likewise, the fastener (150) which holds the tapered contact elements in mating relationship with the conductive rims may take any of numerous forms. All that is required is that the fastener (150) couples to both the circuit board (130) and the integrated circuit package (10), and that the integrated circuit package (10) be removable from the fastener (150).
摘要翻译：集成电路封装（10）设置有多个接触元件引线（91），每个引线具有用于与集成电路（130）进行电连接的第一部分和用于与集成电路（130）电连接的第二锥形接触部分电路板的孔。结合集成电路封装（10），提供了紧固件（150），用于将锥形接触元件（91）与导电边缘保持配合关系。集成电路封装的引线的锥形接触部分可以采用各种形式，只要引线是锥形和弹性的，从而可以实现与导电边缘的适当配合。类似地，将锥形接触元件保持与导电轮辋配合关系的紧固件（150）可以采取任何多种形式。所需要的是紧固件（150）耦合到电路板（130）和集成电路封装（10），并且集成电路封装（10）可从紧固件（150）移除。

3. 发明申请

WO1992014306A1 APPARATUS AND METHODS EMPLOYING DISTRIBUTION PRESERVING TOMLINSON PRECODING IN TRANSMISSION OF DIGITAL DATA SIGNALS 审中-公开
标题翻译：使用数字信号传输方式保存TOMLINSON预分配的方法和方法
公开(公告)号：WO1992014306A1
公开(公告)日：1992-08-20
申请号：PCT/US1992000941
申请日：1992-02-06
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , COLE, Paul, Dana
IPC分类号： H04B01/10
CPC分类号： H03M13/256 , H03M13/25 , H04L25/03343 , H04L25/49 , H04L25/497 , H04L25/4975 , H04L27/34 , H04L27/3461 , H04L2025/03802
摘要： A transmitter (10) is provided with a distribution preserving Tomlinson coder (25) which predistorts shaped data signals (20) such that the power of each data signal exiting the coder is substantially similar to the power of the data signal entering the coder and such that upon transmission of the predistorted data signal over a channel (40), the effect of ISI of the channel is substantially removed. The transmitter is primarily intended for coded modulation systems utilizing a ''coset'' code, and the predistortion is preferably accomplished according to a linear function (1), where rk is a data signal entering the coder, a1 and b1 are the coefficients of polynomials relating to the channel impulse response, xk is the predistorted data signal exiting the coder, and sk is chosen to cause the signal power of xk on average to approximately equal the signal power of rk on average. Different methods for so choosing sk are disclosed. Receivers (50) which cooperate with the provided transmitters (10) are also provided.

4. 发明申请

WO1997013346A1 ATM SWITCH WITH VC PRIORITY BUFFERS 审中-公开
标题翻译： ATM开关与VC优先缓冲区
公开(公告)号：WO1997013346A1
公开(公告)日：1997-04-10
申请号：PCT/US1996015737
申请日：1996-10-02
申请人： GENERAL DATACOMM, INC. , JONES, Trevor
发明人： GENERAL DATACOMM, INC.
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/1523 , H04L49/20 , H04L49/3009 , H04L49/3081 , H04L49/508 , H04L49/552 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： An ATM switch (10) has a plurality of link controllers (12) each having a FIFO (30) for each VC established and a FIFO (32) for each priority level. Cells are pushed into the VC FIFO (30) and a pointer to the VC FIFO (30) is pushed into an arbitration FIFO (32) for the priority level of the VC FIFO (30). The arbitration FIFOs (32) are examined according to a schedule and cells are popped up from VC FIFOs (30) according to priority for exit from the controller (12). According to one embodiment, the highest priority arbitration FIFO (32a) is always examined first and none of the lower priority arbitration FIFOs (32b-32d) are examined unless the highest priority arbitration FIFO is empty. According to another embodiment, timers are set for the lower priority arbitration FIFOs (32b-32d) and if a timer expires for a lower priority arbitration FIFO, it is examined.
摘要翻译： ATM交换机（10）具有多个链路控制器（12），每个链路控制器具有用于每个建立的VC的FIFO（30）和用于每个优先级的FIFO（32）。单元被推入VC FIFO（30），并且指向VC FIFO（30）的指针被推入用于VC FIFO（30）的优先级的仲裁FIFO（32）。根据调度检查仲裁FIFO（32），并且根据从控制器（12）退出的优先级，从VC FIFO（30）弹出单元。根据一个实施例，始终检查最高优先权仲裁FIFO（32a），并且除非最高优先权仲裁FIFO为空，否则不检查低优先权仲裁FIFO（32b-32d）。根据另一个实施例，针对较低优先权的仲裁FIFO（32b-32d）设置定时器，并且如果针对较低优先权的仲裁FIFO的定时器期满，则对其进行检查。

5. 发明申请

WO1996039759A1 CONTROLLING THE FLOW OF ATM CELLS IN AN ATM NETWORK 审中-公开
标题翻译：控制ATM网络中ATM信元的流量
公开(公告)号：WO1996039759A1
公开(公告)日：1996-12-12
申请号：PCT/US1996008906
申请日：1996-06-05
申请人： GENERAL DATACOMM, INC. , JONES, Trevor
发明人： GENERAL DATACOMM, INC.
IPC分类号： H04J01/16
CPC分类号： H04L49/506 , H04L12/5602 , H04L49/205 , H04L49/30 , H04L49/3081 , H04L49/503 , H04L2012/5616 , H04L2012/5635 , H04L2012/5636 , H04L2012/5652 , H04L2012/5682
摘要： Method of controlling flow of ATM cells by signalling to the source of cells on a connection to reduce transmission rate when congestion occurs in a switch in an ATM network. The step of signalling being carried out by way of inserting into the Resource Management cells a new Explicit Rate ER value (28) for the connection at a given point in the network. The ER value being obtained is a function of the number of Available Bit Rate (ABR) cells output from the buffer in an interval. The method includes determining the Number of ABR Virtual Containers VCs with more than a predetermined number of cells stored, determining the number of cells on the connection stored, determining the total number of cells currently stored and the remaining capacity of the buffer, and calculating the ER value from a given formula.
摘要翻译：通过在ATM网络中的交换机中发生拥塞时，通过信令向连接上的小区源控制ATM信元的流量来降低传输速率的方法。信令的步骤是通过向网络中的给定点插入到资源管理单元中的新的显式速率ER值（28）来进行的。获得的ER值是在间隔中从缓冲器输出的可用比特率（ABR）单元的数量的函数。该方法包括：确定存储有多个预定数量的小区的ABR虚拟容器VC的数量，确定存储的连接上的小区数，确定当前存储的小区的总数和缓冲区的剩余容量，以及计算来自给定公式的ER值。

6. 发明申请

WO1994017612A1 DISTRIBUTED FRAME PROCESSING FOR TIME DIVISION MULTIPLEXING 审中-公开
标题翻译：用于时分多路复用的分布式帧处理
公开(公告)号：WO1994017612A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000734
申请日：1994-01-19
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , KURDZO, James, P. , KATZE, Alan, B., Jr.
IPC分类号： H04J03/04
CPC分类号： H04L12/52 , H04J3/0685 , H04J3/1641 , Y10S370/914
摘要： A time division multiplexer is provided for multiplexing data from a plurality of channels. The TDM system generally comprises a high speed time division multiplexed data bus (106), a synchronizing bus (104), a plurality of channel cards (112-116) coupled between the data channels and the data bus with each channel card having its own processor and memory, and a communication manager (120) which is also coupled to the digital bus, and includes a (micro)processor (130). The processor of the SCM determines the frame for the system and initially forwards the frame information to each of the channel cards during predetermined time slots of the high speed data bus. The channel cards are synchronized by the SCM (120) via the synchronization bus (104), and the channel cards use the synchronization information and framing information in order to appropriately place data on and take data off the high speed bus without the use of an address bus.
摘要翻译：提供了一种时分复用器，用于复用来自多个信道的数据。 TDM系统通常包括高速时分复用数据总线（106），同步总线（104），耦合在数据信道和数据总线之间的多个通道卡（112-116），每个通道卡具有其自己的处理器和存储器，以及还耦合到数字总线的通信管理器（120），并且包括微处理器（130）。 SCM的处理器确定系统的帧，并且在高速数据总线的预定时隙期间最初将帧信息转发到每个信道卡。信道卡通过同步总线（104）由SCM（120）同步，并且信道卡使用同步信息和成帧信息，以便适当地将数据放在高速总线上并从数据中取出数据，而不使用地址总线

7. 发明申请

WO1991019362A1 METHOD AND APPARATUS FOR MAPPING AN EIGHT DIMENSIONAL CONSTELLATION OF A CONVOLUTIONALLY CODED COMMUNICATION SYSTEM 审中-公开
标题翻译：用于映射漫游编码通信系统的一个维度的方法和装置
公开(公告)号：WO1991019362A1
公开(公告)日：1991-12-12
申请号：PCT/US1991003964
申请日：1991-06-05
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , GOLDSTEIN, Yuri
IPC分类号： H04B07/02
CPC分类号： H04L27/34 , H04L27/3411
摘要： A mapping technique for a mapper (30) utilizes 29 bits for defining all points of an 8D constellation which is comprised of a desired subset of a concatenation of four 2D constellations, where each 2D constellation has 160 or 192 points. The mapping technique generally comprises: dividing each 2D constellation into 5 or 6 different energy groups of 32 points each, the concatenation of four groups, one from each 2D constellation, comprising an 8D grouping; choosing 512 8D groupings from the possible 5?4 (or 64¿) 8D groupings available; partitioning each group of 32 points into four subgroups, each subgroup of a group being a 90, 180, or 270 degree rotation of a first particular subgroup of the group; and defining each 8D constellation point by using 9 bits to choose the 8D grouping, 8 bits to choose four subgroups in the 8D grouping, one for each 2D constellation, and 12 bits to choose four 2D points, one in each chosen subgroup, the four 2D points comprising the 8D point. The chosen 512 8D groups are preferably the lowest energy 8D groupings.

8. 发明申请

WO1990016097A1 ELECTRICAL CONNECTOR FOR DIRECT CONNECTION TO PLATED THROUGH HOLES IN CIRCUIT BOARD 审中-公开
标题翻译：电气连接器，用于直接连接到电路板中的电极
公开(公告)号：WO1990016097A1
公开(公告)日：1990-12-27
申请号：PCT/US1990003298
申请日：1990-06-11
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , REYMOND, Welles, K. , SORRENTINO, Gregory, L.
IPC分类号： H01R23/70
CPC分类号： H01R12/58 , H05K2201/10393 , H05K2203/176 , Y10T29/49218
摘要： A pluggable electrical connector (10) is provided having contact elements (20) with first ends (32) soldered to a daughter board (40), mid-sections (36) which are crimped and bent through ninety degrees, and second ends (34) which have a converging portion and which terminate in bifurcated conical contact portions (38) which make contact with the rims of contact-quality plated through holes (51) of a mother board (50). By causing contact between the rim and the cone surface, normal forces greater than the mating force are generated. The connector housing (30) includes self-centering funnel openings (66) adjacent the mother board for centering the converging portions (37) of the contact elements (20) therein in a nominal position and for acting as a preloading stop. The housing also includes side-wall locking tabs (72) which hold adjacent rows of contacts at identical fixing points relative to the ninety-degree bend to ensure identical spring parameters for all contact elements.

9. 发明申请

WO1996034469A1 A TRAFFIC SHAPING ATM NETWORK SWITCH 审中-公开
标题翻译：交通形状ATM网络交换机
公开(公告)号：WO1996034469A1
公开(公告)日：1996-10-31
申请号：PCT/US1996005606
申请日：1996-04-22
申请人： GENERAL DATACOMM, INC. , JONES, Trevor
发明人： GENERAL DATACOMM, INC.
IPC分类号： H04J03/16
CPC分类号： H04L49/503 , H04L49/30
摘要： An ATM network switch includes a switch fabric (14), and a plurality of slot controllers (11) coupled to the switch fabric. Each slot controller has at least one external data link (12, 13), cell receiving circuitry (21) for receiving ATM cells from the data link and cell transmitting circuitry (22) for transmitting ATM cells outwardly on the data link. The cell transmitting circuitry of each slot controller includes traffic shaping circuitry (23) arranged to set, for each cell presented to the transmitting circuitry, a current onward transmission time where onward transmission at the input rate meets a predetermined flow rate criterion, and a delayed onward transmission time where onward transmission at the current time would cause the traffic on a VC to exceed a predetermined flow rate criterion. The traffic shaping circuitry includes a buffer (24) which stores each new cell at an address corresponding to the onward transmission time, and output logic (32 or 44) for outputting cells from the buffer at a time corresponding to the address thereof.
摘要翻译： ATM网络交换机包括交换结构（14）和耦合到交换结构的多个时隙控制器（11）。每个时隙控制器具有至少一个外部数据链路（12,13），用于从数据链路接收ATM信元的小区接收电路（21）和用于在数据链路上向外发送ATM信元的小区发送电路（22）。每个时隙控制器的小区发送电路包括流量整形电路（23），其被配置为针对呈现给发送电路的每个小区，设定当前的向前发送时间，其中输入速率向前的发送满足预定流率准则，并且延迟向前传输时间，其中当前时间的向前传输将导致VC上的业务超过预定流量标准。流量整形电路包括一个缓冲器（24），其将每个新的单元存储在与向前发送时间相对应的地址上;以及输出逻辑（32或44），用于在对应于其地址的时间从缓冲器输出单元。

10. 发明申请

WO1994023475A1 SPRING BIASED TAPERED CONTACT ELEMENT 审中-公开
标题翻译：弹簧偏心接触元件
公开(公告)号：WO1994023475A1
公开(公告)日：1994-10-13
申请号：PCT/US1994003393
申请日：1994-03-29
申请人： GENERAL DATACOMM, INC.
发明人： GENERAL DATACOMM, INC. , REYMOND, Welles, K.
IPC分类号： H01R23/72
CPC分类号： H01R4/5016 , H01L24/72 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/30107 , H01R4/48 , H01R12/52 , H01R12/585 , H01R12/712 , H01R12/714 , H01R13/2478 , H01R43/16 , H05K3/325 , H05K2201/10393 , H05K2203/176
摘要： A contact element (10) for an electrical connector or an integrated circuit which is used with a hold-down mechanism has a base portion (18), a spring portion (20) having at least partially helical spring elements, and a tapered contact portion (16) which mates in a biased manner with the conductive rim (22) of a hole (26). The contact element is particularly useful for surface mount applications. The spring portion is preferably arranged with a partially helical spring configuration so that compression of the spring also effects a torsional rotation of the contact portion. The contact element can be fabricated from: a flat sheet with punching, rolling, and/or forming operations, thin walled drawn parts, or modular parts.
摘要翻译：用于电连接器或与压紧机构一起使用的集成电路的接触元件（10）具有基部（18），具有至少部分螺旋弹簧元件的弹簧部分（20）和锥形接触部分（16），其以偏置的方式与孔（26）的导电边缘（22）配合。接触元件对于表面贴装应用特别有用。弹簧部分优选地布置有部分螺旋弹簧构造，使得弹簧的压缩也实现接触部分的扭转旋转。接触元件可以由：具有冲压，轧制和/或成形操作的平板，薄壁拉伸部件或模块部件制成。

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