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1. 发明专利

TWI313460B 用以利用非揮發性浮動閘極記憶體單元以模擬電氣可抹除可程式化唯讀記憶體之方法及裝置 METHOD AND APPARATUS FOR EMULATING AN ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) USING NON-VOLATILE FLOATING GATE MEMORY CELLS 有权
简体标题：用以利用非挥发性浮动闸极内存单元以仿真电气可抹除可进程化唯读内存之方法及设备 METHOD AND APPARATUS FOR EMULATING AN ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) USING NON-VOLATILE FLOATING GATE MEMORY CELLS
公开(公告)号：TWI313460B
公开(公告)日：2009-08-11
申请号：TW093100538
申请日：2004-01-09
申请人：伊姆辛美國有限公司 EMOSYN AMERICA, INC.
发明人：大衛蘇沃德 SOWARDS, DAVID , 特利弗比利斯 BLYTH, TREVOR , 珊尼C 哈默 HOLLMER, SHANE C.
IPC分类号： G11C
CPC分类号： G11C16/0408 , G11C16/0425 , G11C16/08
摘要：本發明揭示一種基於非揮發性浮動閘極記憶體單元(譬如快閃記憶體單元(Flash cell))的模擬EEPROM(電氣可抹除可程式化唯讀記憶體)記憶體陣列,其中一小組位元群共用一共同源極線及多條共同列線,如此以使得該小組位元群可在程式及抹除模式期間充當一用以控制程式干擾及有效持續時間之問題的位元群。共同使用該共用源極線之該等位元構成模擬之EEPROM頁面,該頁面為無需干擾其他位元即可被抹除及重新程式化的最小單元。將該記憶體陣列實體上分成多個行群。一實施例使用四個記憶體陣列,每個陣列由32行及512個頁面列組成(所有四個陣列提供之頁面總數為1024個,其中每個頁面具有8個位元組或64個位元)。一全域列解碼器(global row decoder)對主要列進行解碼,且一頁面列驅動器及一頁面源極驅動器啓用構成一特定陣列的個別列及源極。基於待存取之位址及存取模式(抹除、程式或讀取),藉由一頁面列/源極供給解碼器對該等列驅動器及頁面源極驅動器進行解碼。
简体摘要：本发明揭示一种基于非挥发性浮动闸极内存单元(譬如闪存单元(Flash cell))的仿真EEPROM(电气可抹除可进程化唯读内存)内存数组,其中一小组比特群共享一共同源极线及多条共同列线,如此以使得该小组比特群可在进程及抹除模式期间充当一用以控制进程干扰及有效持续时间之问题的比特群。共同使用该共享源极线之该等比特构成仿真之EEPROM页面,该页面为无需干扰其他比特即可被抹除及重新进程化的最小单元。将该内存数组实体上分成多个行群。一实施例使用四个内存数组,每个数组由32行及512个页面列组成(所有四个数组提供之页面总数为1024个,其中每个页面具有8个字节或64个比特)。一全域列译码器(global row decoder)对主要列进行译码,且一页面列驱动器及一页面源极驱动器启用构成一特定数组的个别列及源极。基于待存取之位址及存取模式(抹除、进程或读取),借由一页面列/源极供给译码器对该等列驱动器及页面源极驱动器进行译码。

2. 发明申请

WO2004109754A3 METHOD AND APPARATUS FOR MULTI-MODE OPERATION IN A SEMICONDUCTOR CIRCUIT 审中-公开
公开(公告)号：WO2004109754A3
公开(公告)日：2004-12-16
申请号：PCT/US2004/015310
申请日：2004-05-14
申请人： EMOSYN AMERICA, INC. , DING, Zhimin , HOLLMER, Shane, C. , BARNETT, Philip, C.
发明人： DING, Zhimin , HOLLMER, Shane, C. , BARNETT, Philip, C.
IPC分类号： G06F12/00
摘要： A multi-mode architecture is disclosed for a semiconductor circuit, such as a smart card, microcontroller or another single-chip data processing circuit. The disclosed semiconductor circuit supports at least two modes of operation. A memory management unit restricts each application to a predetermined memory range and enforces certain mode-specific restrictions for each memory partition. In a secure kernel mode, all resources and services on the semiconductor circuit, such as special function registers, are accessible. In an application mode, certain special function registers are not accessible (and thus, the resources associated with such special function registers are also not accessible). The operating system is normally executed in a secure kernel mode, where most, if not all resources are accessible. Likewise, a user application is normally executed in a user mode, where certain resources are not accessible. If an application attempts to access a restricted resource in a user mode, a fault interrupt is generated. If a user application needs to access a restricted resource that is only available in the kernel mode, the user application invokes the kernel mode using an interrupt.

3. 发明授权

US06970386B2 Method and apparatus for detecting exposure of a semiconductor circuit to ultra-violet light 有权
标题翻译：用于检测半导体电路对紫外光的曝光的方法和装置
公开(公告)号：US06970386B2
公开(公告)日：2005-11-29
申请号：US10378414
申请日：2003-03-03
申请人： Shane C. Hollmer
发明人： Shane C. Hollmer
IPC分类号： G11C16/18 , G11C16/22 , G11C16/04
CPC分类号： G11C16/18 , G11C16/22
摘要： A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The security violation signal may optionally initiate a routine to clear sensitive data from memory or prevent the semiconductor circuit from further operation. The ultra-violet light detection circuit detects whether a semiconductor circuit has been exposed to ultra-violet light, for example, by employing a dedicated mini-array of non-volatile memory cells. At least two active bit lines, blprg and bler, are employed corresponding to program and erase, respectively. One of the bit lines is only programmable and the other bit line is only eraseable. Generally, all of the bits in the dedicated non-volatile memory array are initially in approximately the same state, which could be erased, programmed or somewhere in between. An offset current is added to one bit line and a change in the resulting current difference is used to detect an exposure to ultra-violet light.
摘要翻译：公开了一种用于检测半导体电路是否已经暴露于紫外光的方法和装置。紫外光检测电路检测到紫外光的曝光，并自动激活安全违规信号。安全违规信号可以可选地启动例程以从存储器清除敏感数据或防止半导体电路进一步操作。紫外光检测电路例如通过采用非易失性存储单元的专用微型阵列来检测半导体电路是否已经暴露于紫外光。对应于编程和擦除分别使用至少两个有效位线blprg和bler。其中一个位线只能编程，另一个位线只能擦除。通常，专用非易失性存储器阵列中的所有位最初处于大致相同的状态，这可能被擦除，编程或其间的某处。偏移电流被添加到一个位线，并且所得到的电流差的变化用于检测对紫外光的曝光。

4. 发明授权

US07071763B2 Transistor circuits for switching high voltages and currents without causing snapback or breakdown 有权
标题翻译：用于切换高电压和电流的晶体管电路，而不会导致快速恢复或故障
公开(公告)号：US07071763B2
公开(公告)日：2006-07-04
申请号：US10378413
申请日：2003-03-03
申请人： Trevor Blyth
发明人： Trevor Blyth
IPC分类号： H03K17/687 , H03K17/08
CPC分类号： H03K17/122 , H03K17/102
摘要： A switching circuit is disclosed for switching high voltages and high currents, if necessary, without causing snapback or breakdown. The disclosed high voltage, high current switching circuit comprises a first set of series-connected transistors that includes a plurality of transistors to switch a high voltage without inducing snapback or breakdown; and a second set of series-connected transistors that includes one or more transistors to switch a high current. The first and second sets of series-connected transistors are connected in parallel. The gates of the second set of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector is connected to an output of the first and second sets of series-connected transistors. The output of the voltage detector is coupled to the enabling means.
摘要翻译：公开了一种切换电路，用于在必要时切换高电压和高电流，而不会引起回跳或击穿。所公开的高电压，大电流开关电路包括第一组串联连接的晶体管，其包括多个晶体管以切换高电压而不引起快速恢复或击穿; 以及第二组串联连接的晶体管，其包括用于切换高电流的一个或多个晶体管。第一组和第二组串联晶体管并联连接。第二组串联晶体管的栅极能够引起通过第二组串联晶体管的导通。此外，电压检测器连接到第一和第二组串联晶体管的输出端。电压检测器的输出耦合到启用装置。

5. 发明授权

US07032064B2 Single chip embedded microcontroller having multiple non-volatile erasable PROMS sharing a single high voltage generator 有权
公开(公告)号：US07032064B2
公开(公告)日：2006-04-18
申请号：US10376682
申请日：2003-02-28
申请人： Philip C. Barnett , David Sowards
发明人： Philip C. Barnett , David Sowards
IPC分类号： G06F12/00
CPC分类号： G11C16/30
摘要： A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

6. 发明授权

US06950336B2 Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells 有权
标题翻译：用于使用非易失性浮动栅极存储单元来仿真电可擦除可编程只读存储器（EEPROM）的方法和装置
公开(公告)号：US06950336B2
公开(公告)日：2005-09-27
申请号：US10340342
申请日：2003-01-10
申请人： David Sowards , Trevor Blyth , Shane C. Hollmer
发明人： David Sowards , Trevor Blyth , Shane C. Hollmer
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/0408 , G11C16/0425 , G11C16/08
摘要： An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).
摘要翻译：公开了一种基于诸如闪存单元的非易失性浮动栅极存储器单元的模拟EEPROM存储器阵列，其中一小组位共享公共源极线和公共行线，使得该小组位可被视为在编程和擦除模式下组合，以控制程序干扰和有效耐力的问题。共享源线通用的位构成仿真EEPROM页面，它是可以擦除和重新编程的最小单元，而不会干扰其他位。存储器阵列在物理上分成几组。一个实施例采用四个存储器阵列，每个存储器阵列由32列和512页行组成（所有四个阵列提供总共1024页，每页具有8字节或64位）。全局行解码器对主要行进行解码，并且页面行驱动程序和页面源驱动程序启用组成给定数组的各个行和源。基于要访问的地址和访问模式（擦除，编程或读取），页面行驱动器和页面源驱动器由页面行/源供应解码器进行解码。

7. 发明授权

US07132873B2 Method and apparatus for avoiding gated diode breakdown in transistor circuits 有权
标题翻译：用于避免晶体管电路中栅极二极管击穿的方法和装置
公开(公告)号：US07132873B2
公开(公告)日：2006-11-07
申请号：US10338551
申请日：2003-01-08
申请人： Shane C. Hollmer
发明人： Shane C. Hollmer
IPC分类号： H03K5/08
CPC分类号： H01L27/0266
摘要： An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot. The drain voltage of MXU0 will be at least one N-channel threshold, Vtn, lower than the input voltage level, nprot, and the drain voltage Vd of the bottom N-channel transistor, MXU1, is limited to less than the breakdown voltage, Vbreakdown.
摘要翻译：公开了一种N沟道晶体管保护电路和方法，其防止在其漏极上具有高电压的N沟道晶体管中门控二极管击穿。所公开的N沟道保护电路可以在高电压电平和较低电压电压之间的高电压模式下切换。高电压转换电路通过将两个N沟道晶体管MXU0和MXU1之间的高电压分压来防止N沟道晶体管中的栅极二极管击穿，使得没有晶体管超过击穿电压，V < 。中间电压驱动顶部的N沟道晶体管MXU 0。顶部的N沟道晶体管MXU 0被门控，其电压电平至少为低于高电压电平V SUB的至少一个N沟道阈值V IN Tn ，使用中间电压电平，nprot。 MXU 0的漏极电压将至少比N输入电压电平NOUT和漏极电压V SUB小于N个通道阈值V SUB，底部N沟道晶体管MXU 1被限制为小于击穿电压V分压。

8. 发明授权

US06988231B2 On-chip method and apparatus for testing semiconductor circuits 有权
公开(公告)号：US06988231B2
公开(公告)日：2006-01-17
申请号：US09809897
申请日：2001-03-16
申请人： Philip C. Barnett
发明人： Philip C. Barnett
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/2635 , G01R31/3187
摘要： A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

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