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1. 发明专利

AU2003272313A1 APPARATUS AND METHOD FOR ADDING MULTIPLE-BIT BINARY STRINGS 未知
公开(公告)号：AU2003272313A1
公开(公告)日：2004-04-30
申请号：AU2003272313
申请日：2003-09-09
申请人： ANALOG DEVICE INC
发明人： JALFON MICHEL
IPC分类号： G06F7/50 , G06F7/509 , G06F7/00
摘要： Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.

2. 发明专利

AU2003272313A8 Apparatus and method for adding multiple-bit binary strings 未知
公开(公告)号：AU2003272313A8
公开(公告)日：2004-04-30
申请号：AU2003272313
申请日：2003-09-09
申请人： ANALOG DEVICE INC
发明人： JALFON MICHEL
IPC分类号： G06F7/50 , G06F7/509
摘要： Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.

3. 发明申请

WO2012170243A1 TWO-WIRE DIGITAL AUDIO INTERFACE 审中-公开
标题翻译：双线数字音频接口
公开(公告)号：WO2012170243A1
公开(公告)日：2012-12-13
申请号：PCT/US2012/039928
申请日：2012-05-30
申请人： ANALOG DEVICE, INC. , FU, Jie , PAN, Yang , WU, Yongyi , NGUYEN, Khiem, Quang
发明人： FU, Jie , PAN, Yang , WU, Yongyi , NGUYEN, Khiem, Quang
IPC分类号： G06F1/12
CPC分类号： H04H60/04
摘要： A digital audio interface may include two signal inputs to transmit audio data. A first signal line may carry digital serial audio data. The second signal line may carry a word clock signal to differentiate the serial audio data transmitted over the first signal line. In the case of stereo audio data, the word clock signal may correspond to a left-right clock signal and may differentiate audio data intended for a right channel from that intended for a left channel. The audio data may also be differentiated differently depending on the configuration, such as in the case that the transmitted audio data include audio for more than two channels. The word clock signal may be scaled to regenerate a bit clock signal used to encode the serial audio data over the first signal line. The encoding bit clock signal need not be transmitted.
摘要翻译：数字音频接口可以包括用于传输音频数据的两个信号输入。第一条信号线可以携带数字串行音频数据。第二信号线可以携带字时钟信号以区分通过第一信号线发送的串行音频数据。在立体声音频数据的情况下，字时钟信号可以对应于左右时钟信号，并且可以区分用于右声道的音频数据与用于左声道的音频数据。音频数据也可以根据配置而不同地进行区分，诸如在所发送的音频数据包括多于两个声道的音频的情况下。字时钟信号可以被缩放以再生用于对第一信号线上的串行音频数据进行编码的位时钟信号。编码位时钟信号不需要传输。

4. 发明申请

WO2009117687A1 SYSTEM AND METHOD FOR CAPTURING AN EVENT IN MEMS INERTIAL SENSORS 审中-公开
标题翻译：用于在MEMS惯性传感器中捕获事件的系统和方法
公开(公告)号：WO2009117687A1
公开(公告)日：2009-09-24
申请号：PCT/US2009/037850
申请日：2009-03-20
申请人： ANALOG DEVICE, INC. , LEE, James, M.
发明人： LEE, James, M.
IPC分类号： G01P15/18 , G01P15/08 , G01P1/12 , G11B19/04
CPC分类号： G01P15/18 , G01P1/127 , G01P15/0891 , G11B19/043
摘要： A method of capturing an event in a MEMS accelerometer stores acceleration data in memory, detects a trigger event based on the acceleration data, and modifies a configuration of the memory so that a specified amount of the acceleration data is saved. A MEMS event capturing system includes an inertial sensor having sensor circuitry and event capturing circuitry implemented with the sensor circuitry. The event capturing circuitry includes memory capable of storing acceleration data received from the inertial sensor and a detection module operatively coupled with the memory that detects a trigger event. The event capturing circuitry also includes a management module operatively coupled with the memory and the detection module that modifies the memory's storage configuration when the trigger event is detected.
摘要翻译：在MEMS加速度计中捕获事件的方法将加速度数据存储在存储器中，基于加速度数据检测触发事件，并修改存储器的配置，从而保存指定量的加速数据。 MEMS事件捕获系统包括惯性传感器，其具有用传感器电路实现的传感器电路和事件捕获电路。事件捕获电路包括能够存储从惯性传感器接收的加速度数据的存储器和与该存储器可操作地耦合以检测触发事件的检测模块。事件捕获电路还包括与存储器可操作地耦合的管理模块和当检测到触发事件时修改存储器的存储配置的检测模块。

5. 发明申请

WO2007075885A2 METHODS AND APPARATUS FOR PROGRESSIVE SCANNING OF INTERLACED VIDEO 审中-公开
标题翻译：用于顺序扫描互动视频的方法和设备
公开(公告)号：WO2007075885A2
公开(公告)日：2007-07-05
申请号：PCT/US2006048787
申请日：2006-12-21
申请人： ANALOG DEVICE INC , PAN GUOLIN , LIS FABIAN
发明人： PAN GUOLIN , LIS FABIAN
IPC分类号： H04N5/44
CPC分类号： H04N7/012 , H04N7/0137
摘要： A method for deinterlacing an interlaced video signal is provided which employs a median single edge based line average field interpolation algorithm. The algorithm employs a median filter to determine whether motion occurred between scanning two fields of an interlaced frame and, based on the results, reconstructing intermediate lines in the display frame. The median performs a median computation by determining whether a target pixel value is a median value, rather than computing the median value and determining whether the target pixel value is equal to the computed median.
摘要翻译：提供了一种用于对隔行视频信号进行去隔行的方法，其采用基于中值单边缘的线平均场内插算法。该算法使用中值滤波器来确定在扫描隔行帧的两个场之间是否发生运动，并基于结果重建显示帧中的中间行。中值通过确定目标像素值是否为中值来执行中值计算，而不是计算中值并确定目标像素值是否等于计算的中值。

6. 发明申请

WO2007075885A3 METHODS AND APPARATUS FOR PROGRESSIVE SCANNING OF INTERLACED VIDEO 审中-公开
公开(公告)号：WO2007075885A3
公开(公告)日：2007-07-05
申请号：PCT/US2006/048787
申请日：2006-12-21
申请人： ANALOG DEVICE, INC. , PAN, Guolin , LIS, Fabian
发明人： PAN, Guolin , LIS, Fabian
IPC分类号： H04N5/44
摘要： A method for deinterlacing an interlaced video signal is provided which employs a median single edge based line average field interpolation algorithm. The algorithm employs a median filter to determine whether motion occurred between scanning two fields of an interlaced frame and, based on the results, reconstructing intermediate lines in the display frame. The median performs a median computation by determining whether a target pixel value is a median value, rather than computing the median value and determining whether the target pixel value is equal to the computed median.

7. 发明申请

WO2004025453A2 APPARATUS AND METHOD FOR ADDING MULTIPLE-BIT BINARY STRINGS 审中-公开
标题翻译：用于添加多位二进制字符串的装置和方法
公开(公告)号：WO2004025453A2
公开(公告)日：2004-03-25
申请号：PCT/US2003/028393
申请日：2003-09-09
申请人： ANALOG DEVICE, INC.
发明人： JALFON, Michel
IPC分类号： G06F7/00
CPC分类号： G06F7/509 , G06F7/4991
摘要： Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising : a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.
摘要翻译：用于确定添加至少三个n位数据输入的值，符号和溢出状态的装置。所述设备包括：第一加法器，用于添加所述至少三个n位数据输入，以提供具有至少2n位的第一输出; 第二加法器，用于添加第一输出的一部分比特，第二加法器可操作以添加多个m比特加数，m小于或等于n。该设备还包括至少两个电子电路，其与第一加法器和第二加法器可操作地相关联。第一加法器，第二加法器和至少两个电子电路被构造和设计成使用与奇偶校验相关联的预定奇偶校验规则来获得值，溢出状态和至少三个数据输入的相加的符号至少三个数据输入的特征。

8. 发明申请

WO2011094095A1 IMPROVED HIGH SPEED CHARGE PUMP 审中-公开
标题翻译：改进的高速充电泵
公开(公告)号：WO2011094095A1
公开(公告)日：2011-08-04
申请号：PCT/US2011/021621
申请日：2011-01-19
申请人： ANALOG DEVICE, INC. , MOORE, Ralph
发明人： MOORE, Ralph
IPC分类号： H03L7/06
CPC分类号： H03L7/091 , H03L7/0812 , H03L7/087 , H03L7/0893 , H03L7/0895 , H03L7/0896
摘要： In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage.
摘要翻译：在一个实施例中，主电荷泵和复制电荷泵可以耦合到匹配的控制机构和负载。在一个实施例中，复制电荷泵可以在稳定的锁定环路状态下产生源自电荷泵定时失配的误差电流。由复制电荷泵产生的误差电流可以由差分放大器来测量，以调整至少一个电流源来补偿由定时失配引起的误差电流。为了调整电流源，放大器可能导致电流源产生相等但相反的电流，以消除误差电流的影响，导致恒定的输出电压。

9. 发明申请

WO2007147891A1 DIGITAL-TO-ANALOG CONVERTER WITH CONTROLLED BUFFERED INPUTS 审中-公开
标题翻译：具有控制缓冲输入的数字到模拟转换器
公开(公告)号：WO2007147891A1
公开(公告)日：2007-12-27
申请号：PCT/EP2007/056253
申请日：2007-06-22
申请人： ANALOG DEVICE, INC. , COSGRAVE, Gavin
发明人： COSGRAVE, Gavin
IPC分类号： H03M1/06 , H03M1/68 , H03M1/66
CPC分类号： H03M1/0612 , H03M1/662 , H03M1/687
摘要： A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.
摘要翻译：提供DAC电路，其实现缓冲DAC输入，其中缓冲器由差分放大器提供，其差分放大器的电源轨与DAC的输入相关。以这种方式，可以使用放大器对电路进行缓冲，其开环增益规格可以放宽，而不影响DAC的线性性能。

10. 发明公开

US20240012054A1 TECHNIQUE FOR ESTIMATION OF INTERNAL BATTERY TEMPERATURE 审中-公开
公开(公告)号：US20240012054A1
公开(公告)日：2024-01-11
申请号：US18044550
申请日：2021-07-21
申请人： Analog Device, Inc.
发明人： Frank M. Yaul , Sunrita Poddar , Hemtej Gullapalli , Omer Tanovic
IPC分类号： G01R31/367 , G01R31/382 , G01R31/389 , G01R31/392 , G01K7/42
CPC分类号： G01R31/367 , G01R31/382 , G01R31/389 , G01R31/392 , G01K7/427 , G01K2217/00
摘要： One embodiment is a method for estimating an internal temperature of a battery, the method comprising obtaining multiple terminal impedance measurements, wherein each of the terminal impedance measurements is taken at a different one of a plurality of frequencies; determining model parameters for a multivariable polynomial regression model; and applying the multivariable polynomial regression model to the multiple terminal impedance measurements to estimate the internal temperature of the battery.

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