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1. 发明申请

WO2011053482A1 A DIGITAL-TO-ANALOGUE CONVERTER 审中-公开
标题翻译：数字到模拟转换器
公开(公告)号：WO2011053482A1
公开(公告)日：2011-05-05
申请号：PCT/US2010/053180
申请日：2010-10-19
申请人： ANALOG DEVICES, INC. , COSGRAVE, Gavin
发明人： COSGRAVE, Gavin
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765
摘要： An N-bit DAC comprises a main DAC circuit having main nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one MSB value, and a sub-DAC circuit having secondary nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one LSB. A main switch network couples the secondary nodes to a selected pair of main nodes as the MSB value of the digital input signal varies. A secondary switch network selectively couples one of secondary nodes to an output terminal for providing an analogue voltage output signal. The main nodes are coupled between main terminals, and a voltage reference is applied across input terminals. A first offset circuit and a first compensating circuit are selectively coupleable between the main DAC circuit and the input terminals for offsetting the main node analogue voltages downwardly.
摘要翻译： N位DAC包括主DAC电路，其主节点在其上产生逐步增加值的步骤中的一个MSB值的逐步增加的值，以及具有次级节点的子DAC电路，其上逐渐产生模拟电压以一个LSB的值增加值。当数字输入信号的MSB值变化时，主交换机网络将辅助节点耦合到所选择的一对主节点。次级开关网络将二级节点之一选择性地耦合到输出端，以提供模拟电压输出信号。主节点耦合在主终端之间，并且在输入端之间施加电压基准。第一偏移电路和第一补偿电路在主DAC电路和输入端子之间选择性地耦合，用于向下偏移主节点模拟电压。

2. 发明申请

WO2007147891A1 DIGITAL-TO-ANALOG CONVERTER WITH CONTROLLED BUFFERED INPUTS 审中-公开
标题翻译：具有控制缓冲输入的数字到模拟转换器
公开(公告)号：WO2007147891A1
公开(公告)日：2007-12-27
申请号：PCT/EP2007/056253
申请日：2007-06-22
申请人： ANALOG DEVICE, INC. , COSGRAVE, Gavin
发明人： COSGRAVE, Gavin
IPC分类号： H03M1/06 , H03M1/68 , H03M1/66
CPC分类号： H03M1/0612 , H03M1/662 , H03M1/687
摘要： A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.
摘要翻译：提供DAC电路，其实现缓冲DAC输入，其中缓冲器由差分放大器提供，其差分放大器的电源轨与DAC的输入相关。以这种方式，可以使用放大器对电路进行缓冲，其开环增益规格可以放宽，而不影响DAC的线性性能。

3. 发明申请

WO2007147895A1 DIGITAL TO ANALOG CONVERTER WITH SHARED CALIBRATION 审中-公开
标题翻译：数字模拟转换器，具有共享校准
公开(公告)号：WO2007147895A1
公开(公告)日：2007-12-27
申请号：PCT/EP2007/056270
申请日：2007-06-22
申请人： ANALOG DEVICES, INC. , COSGRAVE, Gavin , LYDEN, Colin , MCLACHLAN, Roderick , DEMPSEY, Dennis , VINEREANU, Tudor , KIRBY, Patrick
发明人： COSGRAVE, Gavin , LYDEN, Colin , MCLACHLAN, Roderick , DEMPSEY, Dennis , VINEREANU, Tudor , KIRBY, Patrick
IPC分类号： H03M1/10 , H03M1/66 , H03M1/68
CPC分类号： H03M1/1038 , H03M1/662 , H03M1/68
摘要： Multi-channel DAC with two stages (eg for the MSBs and the LSBs respectively). The first stage is shared by the channels. Calibration coefficients are stored for correcting the digital input data and provide a corrected DC transfer characteristic (eg offset, gain, linearity) of the DAC channels. The calibration coefficients are shared by all the channels or by selected groups of them.
摘要翻译：具有两级的多通道DAC（例如，分别用于MSB和LSB）。第一阶段由频道共享。存储校准系数以校正数字输入数据并提供DAC通道的校正的DC传递特性（例如，偏移，增益，线性度）。校准系数由所有通道或其选定的组共享。

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