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1. 发明公开

EP1492907A4 ELECTROPOLISHING AND/OR ELECTROPLATING APPARATUS AND METHODS 审中-公开
标题翻译：电解抛光和/或电镀和程序
公开(公告)号：EP1492907A4
公开(公告)日：2008-01-09
申请号：EP03746651
申请日：2003-04-08
申请人： ACM RES INC
发明人： WANG HUI , NUCH VOHA , GUTMAN FELIX , AFNAN MUHAMMED , CHOKSHI HIMANSHU J , VAN KERKWYK MARK JACOBUS , KOEHLER DAMON L , YIH PEIHAUR , NGUYEN MY HOANG , CHANG RU KAO , HO FREDERICK
IPC分类号： C25D7/12 , C25D17/06 , C25D19/00 , C25F3/30 , C25F7/00 , H01L21/00 , H01L21/288 , H01L21/304 , H01L21/677 , H01L21/683 , H01L21/687 , C25D5/48 , C25D17/00
CPC分类号： H01L21/6708 , C25D7/12 , C25D17/001 , C25F7/00 , H01L21/2885 , H01L21/67051 , H01L21/67769 , H01L21/6838 , H01L21/68707
摘要： In one aspect of the present invention, exemplary apparatus and methods are provided for electropolishing and/or electroplating processes for semiconductor wafers. One exemplary apparatus includes a cleaning module having an edge clean assembly (930) to remove metal residue on the bevel or edge portion of a wafer (901). The edge cleaning apparatus includes a nozzle head (1030) configured to supply a liquid and a gas to a major surface of the wafer, and supplies the gas radially inward of the location the liquid is supplied to reduce the potential of the liquid from flowing radially inward to the metal film formed on the wafer.

2. 发明申请

WO2006110864A3 METHOD FOR IMPROVING SURFACE ROUGHNESS DURING ELECTRO-POLISHING 审中-公开
标题翻译：在电抛光过程中改善表面粗糙度的方法
公开(公告)号：WO2006110864A3
公开(公告)日：2008-09-25
申请号：PCT/US2006013804
申请日：2006-04-12
申请人： ACM RES INC , WANG HUI , HO FREDRICK , WANG JIAN
发明人： WANG HUI , HO FREDRICK , WANG JIAN
IPC分类号： C25D3/02
CPC分类号： C25F7/00 , B23H5/08 , B24B37/04 , B24B57/02
摘要： A surface is electropolished using a stream of electrolyte. A nozzle is used to apply the stream of electrolyte to the surface. The nozzle has an insulator wall and a partial electrode. The insulator wall and the partial electrode form a flow channel for the stream of electrolyte. The stream of electrolyte contacts the insulator wall and the partial electrode when the stream of electrolyte flows through the flow channel formed by the insulator wall and the partial electrode. The insulator wall is less electrically conductive than the partial electrode. A power supply is connected to the partial electrode. The power supply is configured to apply a charge to the stream of electrolyte through the partial electrode when the stream of electrolyte flows through the flow channel formed by the insulator wall and the partial electrode.
摘要翻译：使用电解质流对表面进行电抛光。使用喷嘴将电解液流施加到表面。喷嘴具有绝缘体壁和部分电极。绝缘体壁和部分电极形成用于电解质流的流动通道。当电解质流过由绝缘体壁和部分电极形成的流动通道时，电解质流与绝缘体壁和部分电极接触。绝缘体壁比部分电极导电性差。电源连接到部分电极。电源构造成当电解质流流过由绝缘体壁和部分电极形成的流动通道时，通过部分电极向电解质流施加电荷。

3. 发明申请

WO2004057648A3 LOCALIZED REFLOW FOR WIRE BONDING AND FLIP CHIP CONNECTIONS 审中-公开
标题翻译：本地化反馈用于线路连接和片式连接
公开(公告)号：WO2004057648A3
公开(公告)日：2005-02-17
申请号：PCT/US0340638
申请日：2003-12-18
申请人： ACM RES INC , WANG HUI
发明人： WANG HUI
IPC分类号： H01L20060101 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/60
CPC分类号： H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/1134 , H01L2224/131 , H01L2224/13111 , H01L2224/48463 , H01L2224/78301 , H01L2224/81801 , H01L2224/85214 , H01L2924/00013 , H01L2924/00014 , H01L2924/01007 , H01L2924/0101 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/16152 , H01L2924/351 , H01L2224/13099 , H01L2224/45099 , H01L2924/00
摘要： A system for soldering electrical connection for a chip (300) includes a bonding pad (302), a solder bump (304), and an energy source (306). The energy source (306) is localized to the solder bump (304) without physically contacting the solder bump (304). Localized energy source (306) heat solder bump (340), to reflow the solder bump (304) on the bonding pad (302) without heating the entire chip (300).
摘要翻译：用于焊接用于芯片（300）的电连接的系统包括接合焊盘（302），焊料凸块（304）和能量源（306）。能量源（306）被定位到焊料凸点（304），而不物理地接触焊料凸块（304）。局部能量源（306）加热焊料凸块（340），以在焊盘（302）上回流焊料凸块（304），而不加热整个芯片（300）。

4. 发明公开

EP1382065A4 ELECTROPOLISHING METAL LAYERS ON WAFERS HAVING TRENCHES OR VIAS WITH DUMMY STRUCTURES 审中-公开
标题翻译：电气工头END金属层在晶片上的沟或与虚拟结构的接触孔
公开(公告)号：EP1382065A4
公开(公告)日：2009-04-15
申请号：EP02764165
申请日：2002-04-04
申请人： ACM RES INC
发明人： WANG HUI , YIH PEIHAUR
IPC分类号： C25F3/30 , H01L21/321 , C25D5/02 , C25D5/48 , C25D7/12 , H01L21/3205 , H01L21/768 , H01L23/48 , H01L23/52
CPC分类号： C25D5/48 , C25D5/02 , C25D7/123 , H01L21/32125 , H01L21/7684
摘要： In electropolishing a metal layer on a semiconductor wafer, a dielectric layer (100) is formed on the semiconductor wafer (not shown). The dielectric layer (100) is formed with a recessed (102) area and a non-recessed (103) area. A plurality of dummy structures (200) are inactive areas configured to increase the planarity of a metal layer (106) subsequently formed on the dielectric layer (100). A metal layer (106) is then formed to fill the recessed (102) area and to cover the non-recessed (103) area and the plurality of dummy structures (200). The metal layer (106) is then electropolished to expose the non-recessed area (102).

5. 发明公开

EP1419523A4 DUMMY STRUCTURES TO REDUCE METAL RECESS IN ELECTROPOLISHING PROCESS 审中-公开
标题翻译：平衡结构用于减少金属凹槽的一个电FOREMAN过程
公开(公告)号：EP1419523A4
公开(公告)日：2007-12-19
申请号：EP02757215
申请日：2002-08-16
申请人： ACM RES INC
发明人： WANG HUI , YIH PEIHAUR
IPC分类号： C25F3/12 , C25D5/02 , C25D7/12 , C25F3/00 , C25F7/00 , H01L21/3205 , H01L21/321 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/528 , H01L23/58 , H01L21/311
CPC分类号： C25D5/02 , C25D5/022 , C25D7/123 , C25F3/00 , H01L21/32115 , H01L21/7684 , H01L23/528 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure for providing metal interconnections (140) and a method for electropolishing a metal layer on a semiconductor structure. A semiconductor structure includes a dielectric layer (151) with recessed areas (151r) and non-recessed areas (151n), a metal layer formed on the structure fills the recessed areas to form interconnection lines, and a plurality of dummy structures (130) placed adjacent the interconnect lines. The method includes forming a dielectric layer with recessed and non-recessed areas on a semiconductor wafer. Forming dummy structures adjacent the recessed areas. Forming a metal layer to cover the dielectric layer and the dummy structures. The metal layer is then electropolished to expose the non-recessed area.

6. 发明申请

WO9941434A3 PLATING APPARATUS AND METHOD 审中-公开
标题翻译：电镀设备和方法
公开(公告)号：WO9941434A3
公开(公告)日：1999-10-14
申请号：PCT/US9900964
申请日：1999-01-15
申请人： ACM RES INC
发明人： WANG HUI
IPC分类号： C25D5/02 , C25D5/08 , C25D5/18 , C25D7/12 , C25D21/12 , H01L21/288 , H01L21/48 , H01L21/768 , H01L23/532
CPC分类号： C25D5/18 , C25D5/026 , C25D5/08 , C25D21/12 , H01L21/4846
摘要： An apparatus for plating a conductive film directly on a substrate with a barrier layer on top includes anode rod (1) placed in tube (109), and anode rings (2, and 3) placed between cylindrical walls (107, 105), (103, 101) respectively. Anodes (1, 2, 3) are powered by power supplies (13, 12 and 11), respectively. Electrolyte (34) is pumped by pump (33) to pass through filter (32) and reach inlets of liquid mass flow controllers (LMFCs) (21, 22, 23). Then LMFCs (21, 22, 23) deliver electrolyte at a set flow rate to sub-plating baths containing anodes (3, 2, 1), respectively. After flowing through the gap between wafer (31) and the top of the cylindrical walls (101, 103, 105, 107 and 109), electrolyte flows back to tank (36) through spaces between cylindrical walls (100, 101), (103, 105), (107, 109), respectively. A pressure leak valve (38) is placed between the outlet of pump (33) and electrolyte tank (36) to leak electrolyte back to tank (36) when LMFCs (21, 22, 23) are closed. A wafer (31) held by wafer chuck (29) is connected to power supplies (11, 12 and 13). A drive mechanism (30) is used to rotate wafer (31) around the z axis, and oscillate the wafer in the x, y, and z directions shown. Filter (32) filters particles larger than 0.1 or 0.2 mu m in order to obtain a low particle added plating process.
摘要翻译：一种用于在顶部具有阻挡层的基板上直接镀覆导电膜的设备包括放置在管（109）中的阳极棒（1）和放置在圆柱形壁（107,105）之间的阳极环（2和3），（ 103,101）。阳极（1,2,3）由电源（13,12和11）分别供电。电解液（34）由泵（33）泵送通过过滤器（32）并到达液体质量流量控制器（LMFC）（21,22,23）的入口。然后，LMFC（21,22,23）以设定的流量将电解液分别递送到含有阳极（3,2,1）的亚镀浴。在流过晶片（31）和圆柱形壁（101,103,105,107和109）的顶部之间的间隙之后，电解液通过圆柱形壁（100,101），（103）之间的空间流回到罐（36），105），（107,109）。当LMFC（21,22,23）关闭时，压力泄漏阀（38）放置在泵（33）的出口和电解液罐（36）之间，以将电解液泄漏回罐（36）。由晶片卡盘（29）保持的晶片（31）连接到电源（11,12,13）。使用驱动机构（30）围绕z轴旋转晶片（31），并且在所示的x，y和z方向上振荡晶片。过滤器（32）过滤大于0.1或0.2μm的颗粒，以获得低的颗粒添加电镀工艺。

7. 发明申请

WO2005082057A3 CONTROLLING REMOVAL RATE UNIFORMITY OF AN ELECTROPOLISHING PROCESS IN INTEGRATED CIRCUIT FABRICATION 审中-公开
标题翻译：一体化电路制造中电解过程的去除速率均匀性的控制
公开(公告)号：WO2005082057A3
公开(公告)日：2009-04-02
申请号：PCT/US2005006142
申请日：2005-02-23
申请人： ACM RES INC , WANG HUI , AFNAN MUHAMMED , WANG JIAN , GUTMAN FELIX , HO FREDERICK , CHOKSHI HIMANSHU J
发明人： WANG HUI , AFNAN MUHAMMED , WANG JIAN , GUTMAN FELIX , HO FREDERICK , CHOKSHI HIMANSHU J
IPC分类号： C25F3/16 , C25F7/00
CPC分类号： B23H5/08 , B24B37/04 , C25F3/02 , C25F5/00 , C25F7/00 , H01L21/32115
摘要： A metal layer formed on a wafer, the wafer having a center portion and an edge portion, is electropolished by aligning a nozzle and the wafer to position the nozzle adjacent to the center portion of the wafer. The wafer is rotated. As the wafer is rotated, a stream of electrolyte is applied from the nozzle onto a portion of the metal layer adjacent to the center portion of the wafer to begin to electropolish the portion of the metal layer with a triangular polishing profile to initially expose an underlying layer underneath the metal layer at a point.
摘要翻译：在晶片上形成的金属层（具有中心部分和边缘部分的晶片）通过对准喷嘴和晶片以将喷嘴定位成与晶片的中心部分相邻来进行电抛光。晶圆旋转。当晶片旋转时，电解质流从喷嘴施加到与晶片的中心部分相邻的金属层的一部分上，以开始以三角抛光轮廓对金属层的部分进行电解，以初始暴露底层在一点上金属层下方的层。

8. 发明申请

WO2005055283A3 MONITORING AN ELECTROPOLISHING PROCESS IN INTEGRATED CIRCUIT FABRICATION 审中-公开
标题翻译：监控整合电路制造中的电镀工艺
公开(公告)号：WO2005055283A3
公开(公告)日：2008-01-31
申请号：PCT/US2004039748
申请日：2004-11-26
申请人： ACM RES INC , WANG HUI , YIP HENRY , WANG JIAN , YU CHAW-CHI
发明人： WANG HUI , YIP HENRY , WANG JIAN , YU CHAW-CHI
IPC分类号： C25F3/00 , C25F3/22 , C25F7/00 , H01L20060101 , H01L21/02 , H01L21/321 , H01L21/70 , H01L21/768
CPC分类号： C25F3/16 , H01L22/14 , H01L22/26
摘要： An electropolishing process of a metal layer formed on a wafer used in integrated circuit fabrication includes rotating the wafer. As the wafer is rotated, a stream of electrolyte is applied through a nozzle to the metal layer at a first radial location on the wafer. The electropolishing process is monitored by measuring electrical resistance at the first radial location. The electrical resistance measured at the first radial location is compared to a first preset electrical resistance associated with the first radial location. An electropolishing charge applied at the first radial location is controlled based on the comparison of the electrical resistance measured at the first radial location to the first preset electrical resistance associated with the first radial location. After applying the stream of electrolyte at the first radial location, the stream of electrolyte is applied at a second radial location. Electrical resistance at the second radial location is measured. The electrical resistance measured at the second radial location is compared to a second preset electrical resistance, which is different than the first preset electrical resistance, associated with the second radial location. The electropolishing charge applied at the second radial location is controlled based on the comparison of the electrical resistance measured at the second radial location to the second preset electrical resistance associated with the second radial location.
摘要翻译：在用于集成电路制造的晶片上形成的金属层的电抛光工艺包括旋转晶片。当晶片旋转时，电晶体流通过喷嘴在晶片上的第一径向位置处施加到金属层。通过测量第一径向位置处的电阻来监测电抛光过程。将在第一径向位置处测量的电阻与与第一径向位置相关联的第一预设电阻进行比较。基于在第一径向位置处测量的电阻与与第一径向位置相关联的第一预设电阻的比较来控制施加在第一径向位置处的电抛光电荷。在第一径向位置施加电解质流之后，在第二径向位置施加电解质流。测量第二径向位置处的电阻。将在第二径向位置处测量的电阻与与第二径向位置相关联的第一预设电阻不同的第二预设电阻进行比较。基于在第二径向位置处测量的电阻与与第二径向位置相关联的第二预设电阻的比较来控制施加在第二径向位置处的电抛光电荷。

9. 发明申请

WO0033356A2 METHODS AND APPARATUS FOR HOLDING AND POSITIONING SEMICONDUCTOR WORKPIECES DURING ELECTROPOLISHING AND/OR ELECTROPLATING OF THE WORKPIECES 审中-公开
标题翻译：在工件电镀和/或电镀过程中保持和定位半导体工件的方法和装置
公开(公告)号：WO0033356A2
公开(公告)日：2000-06-08
申请号：PCT/US9928106
申请日：1999-11-24
申请人： ACM RES INC , WANG HUI , GUTMAN FELIX , NUCH VOHA
发明人： WANG HUI , GUTMAN FELIX , NUCH VOHA
IPC分类号： C25D7/12 , C25D17/06 , C25D17/08 , C25D21/10 , C25F7/00 , H01L21/288 , H01L21/3063 , H01L21/321 , H01L21/687 , H01L
CPC分类号： H01L21/68721 , H01L21/2885 , H01L21/32115 , H01L21/68785 , H01L21/68792
摘要： A wafer chuck assembly for holding a wafer during electroplating and/or electropolishing of the wafer includes a wafer chuck for receiving the wafer. The wafer chuck assembly also includes an actuator assembly for moving the wafer chuck between a first and a second position. When in the first position, the wafer chuck is opened. When in the second position, the wafer chuck is closed.
摘要翻译：用于在晶片的电镀和/或电解抛光期间保持晶片的晶片卡盘组件包括用于接收晶片的晶片卡盘。晶片卡盘组件还包括用于在第一和第二位置之间移动晶片卡盘的致动器组件。当处于第一位置时，打开晶片卡盘。当处于第二位置时，晶片卡盘关闭。

10. 发明申请

WO2004053942A2 MEASURING ALIGNMENT BETWEEN A WAFER CHUCK AND POLISHING/PLATING RECEPTACLE 审中-公开
标题翻译：测量卡盘与抛光/镀覆接头之间的对准
公开(公告)号：WO2004053942A2
公开(公告)日：2004-06-24
申请号：PCT/US0339221
申请日：2003-12-09
申请人： ACM RES INC , WANG HUI , NUCH VOHA
发明人： WANG HUI , NUCH VOHA
IPC分类号： B24B37/04 , B24B47/22 , B24B49/04 , H01L
CPC分类号： B24B37/042 , B24B47/22 , B24B49/04
摘要： An apparatus for electropolishing and/or electroplating metal layers on a semiconductor wafer includes a receptacle having a plurality of section walls. The apparatus includes a wafer chuck configured to hold the semiconductor wafer and to position the semiconductor wafer within the receptacle with a surface of the semiconductor wafer adjacent to top portions of the plurality of section walls. The apparatus also includes a first plurality of sensors configured to measure alignment between the center of one of the plurality of section walls to the center of the wafer chuck, and thus the center of the semiconductor wafer.
摘要翻译：用于在半导体晶片上电解抛光和/或电镀金属层的装置包括具有多个部分壁的插座。该装置包括晶片卡盘，其被配置为保持半导体晶片并且将半导体晶片定位在插座内，其中半导体晶片的表面与多个部分壁的顶部部分相邻。该装置还包括第一多个传感器，其被配置为测量多个部分壁中的一个的中心与晶片卡盘的中心之间的对准，并且因此测量半导体晶片的中心。

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