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1. 发明授权

US08756363B2 Efficient storage of memory version data 有权
标题翻译：高效存储内存版本数据
公开(公告)号：US08756363B2
公开(公告)日：2014-06-17
申请号：US13178240
申请日：2011-07-07
申请人： Zoran Radovic , Graham Ricketson Murphy , Bharat K. Daga
发明人： Zoran Radovic , Graham Ricketson Murphy , Bharat K. Daga
IPC分类号： G06F12/00
CPC分类号： G06F21/52 , G06F11/073 , G06F11/0763 , G06F11/1666
摘要： Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.
摘要翻译：处理器中有效的内存损坏检测的系统和方法。处理器检测将在物理存储器中分配第一数据结构。物理存储器可以是具有为硬件故障切换机制保留的备用存储体的DRAM。处理器或操作系统（OS）都确定与第一数据结构对应的第一版本号。在第一数据结构的初始化期间，第一版本号可以存储在备用存储体中的第一位置。处理器从OS接收保持第一版本号的指针。当处理器执行针对第一数据结构的存储器访问操作时，处理器将第一版本号与存储在由存储器访问地址指示的物理存储器中的位置中的第三版本号进行比较。响应于确定不匹配，处理器可以设置陷阱。

2. 发明申请

US20130013843A1 EFFICIENT STORAGE OF MEMORY VERSION DATA 有权
标题翻译：高效存储内存版本数据
公开(公告)号：US20130013843A1
公开(公告)日：2013-01-10
申请号：US13178240
申请日：2011-07-07
申请人： Zoran Radovic , Graham Ricketson Murphy , Bharat K. Daga
发明人： Zoran Radovic , Graham Ricketson Murphy , Bharat K. Daga
IPC分类号： G06F12/06
CPC分类号： G06F21/52 , G06F11/073 , G06F11/0763 , G06F11/1666
摘要： Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.
摘要翻译：处理器中有效的内存损坏检测的系统和方法。处理器检测将在物理存储器中分配第一数据结构。物理存储器可以是具有为硬件故障切换机制保留的备用存储体的DRAM。处理器或操作系统（OS）都确定与第一数据结构对应的第一版本号。在第一数据结构的初始化期间，第一版本号可以存储在备用存储体中的第一位置。处理器从OS接收保持第一版本号的指针。当处理器执行针对第一数据结构的存储器访问操作时，处理器将第一版本号与存储在由存储器访问地址指示的物理存储器中的位置中的第三版本号进行比较。响应于确定不匹配，处理器可以设置陷阱。

3. 发明授权

US08732430B2 Method and apparatus for using unused bits in a memory pointer 有权
标题翻译：在存储器指针中使用未使用位的方法和装置
公开(公告)号：US08732430B2
公开(公告)日：2014-05-20
申请号：US13069337
申请日：2011-03-22
申请人： Zoran Radovic , Graham Ricketson Murphy , Paul J. Jordan , John G. Johnson
发明人： Zoran Radovic , Graham Ricketson Murphy , Paul J. Jordan , John G. Johnson
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/10 , G06F8/315 , G06F12/02 , G06F12/0253
摘要： The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.
摘要翻译：所公开的实施例提供了使用存储器指针中的未使用位的系统。在操作期间，系统确定地址空间中的一组地址位，在编程操作期间不需要寻址目的。随后，系统将与存储器指针相关联的数据存储在该组地址位中。当使用存储器指针访问与存储器指针相关联的存储器地址时，系统将对该组地址位进行掩蔽。将附加数据存储在未使用的指针位中可以减少程序的存储器访问次数，并提高程序性能和/或可靠性。

4. 发明授权

US08751736B2 Instructions to set and read memory version information 有权
标题翻译：设置和读取内存版本信息的说明
公开(公告)号：US08751736B2
公开(公告)日：2014-06-10
申请号：US13196514
申请日：2011-08-02
申请人： Zoran Radovic , Darryl J. Gove , Graham Ricketson Murphy
发明人： Zoran Radovic , Darryl J. Gove , Graham Ricketson Murphy
IPC分类号： G06F12/02
CPC分类号： G06F11/0763 , G06F9/3824 , G06F9/3834 , G06F9/3851 , G06F11/073
摘要： Systems and methods for providing additional instructions for supporting efficient memory corruption detection in a processor. A physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Version numbers associated with data structures allocated in the memory may be generated so that version numbers of adjacent data structures are different. A processor determines that a fetched instruction is a memory access instruction corresponding to a first data structure within the memory. For instructions that are not a version update instruction, the processor compares the first version number and second version number stored in a location in the memory indicated by the generated address and flags an error if there is a mismatch. For version update instructions, the processor performs a memory access operation on the second version number with no comparison check.
摘要翻译：用于提供用于在处理器中支持有效的内存损坏检测的附加指令的系统和方法。物理存储器可以是DRAM，其具有为硬件故障转移机制保留的备用存储体。可以生成与分配在存储器中的数据结构相关联的版本号，使得相邻数据结构的版本号不同。处理器确定所提取的指令是与存储器内的第一数据结构相对应的存储器访问指令。对于不是版本更新指令的指令，处理器比较存储在由生成的地址指示的存储器中的位置中的第一版本号和第二版本号，并且如果存在不匹配则标记错误。对于版本更新指令，处理器对第二版本号执行存储器访问操作，而不进行比较检查。

5. 发明申请

US20130036276A1 INSTRUCTIONS TO SET AND READ MEMORY VERSION INFORMATION 有权
标题翻译：设置和读取存储器版本信息的说明
公开(公告)号：US20130036276A1
公开(公告)日：2013-02-07
申请号：US13196514
申请日：2011-08-02
申请人： Zoran Radovic , Darryl J. Gove , Graham Ricketson Murphy
发明人： Zoran Radovic , Darryl J. Gove , Graham Ricketson Murphy
IPC分类号： G06F12/00 , G06F9/30
CPC分类号： G06F11/0763 , G06F9/3824 , G06F9/3834 , G06F9/3851 , G06F11/073
摘要： Systems and methods for providing additional instructions for supporting efficient memory corruption detection in a processor. A physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Version numbers associated with data structures allocated in the memory may be generated so that version numbers of adjacent data structures are different. A processor determines that a fetched instruction is a memory access instruction corresponding to a first data structure within the memory. For instructions that are not a version update instruction, the processor compares the first version number and second version number stored in a location in the memory indicated by the generated address and flags an error if there is a mismatch. For version update instructions, the processor performs a memory access operation on the second version number with no comparison check.
摘要翻译：用于提供用于在处理器中支持有效的内存损坏检测的附加指令的系统和方法。物理存储器可以是DRAM，其具有为硬件故障转移机制保留的备用存储体。可以生成与分配在存储器中的数据结构相关联的版本号，使得相邻数据结构的版本号不同。处理器确定所提取的指令是与存储器内的第一数据结构相对应的存储器访问指令。对于不是版本更新指令的指令，处理器比较存储在由生成的地址指示的存储器中的位置中的第一版本号和第二版本号，并且如果存在不匹配则标记错误。对于版本更新指令，处理器对第二版本号执行存储器访问操作，而不进行比较检查。

6. 发明申请

US20120246437A1 METHOD AND APPARATUS FOR USING UNUSED BITS IN A MEMORY POINTER 有权
标题翻译：在存储器中使用未使用位的方法和装置
公开(公告)号：US20120246437A1
公开(公告)日：2012-09-27
申请号：US13069337
申请日：2011-03-22
申请人： Zoran Radovic , Graham Ricketson Murphy , Paul J. Jordan , John G. Johnson
发明人： Zoran Radovic , Graham Ricketson Murphy , Paul J. Jordan , John G. Johnson
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/10 , G06F8/315 , G06F12/02 , G06F12/0253
摘要： The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.
摘要翻译：所公开的实施例提供了使用存储器指针中的未使用位的系统。在操作期间，系统确定地址空间中的一组地址位，在编程操作期间不需要寻址目的。随后，系统将与存储器指针相关联的数据存储在该组地址位中。当使用存储器指针访问与存储器指针相关联的存储器地址时，系统将对该组地址位进行掩蔽。将附加数据存储在未使用的指针位中可以减少程序的存储器访问次数，并提高程序性能和/或可靠性。

7. 发明授权

US08024522B1 Memory ordering queue/versioning cache circuit 有权
标题翻译：内存订购队列/版本控制缓存电路
公开(公告)号：US08024522B1
公开(公告)日：2011-09-20
申请号：US12030851
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/3857 , G06F9/3004 , G06F9/3808 , G06F9/3834 , G06F9/3851 , G06F9/3863 , G06F12/0875 , Y02D10/13
摘要： A processor includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. The circuit also includes a sub-circuit that holds memory operation ordering information corresponding to the active memory operations. The sub-circuit detects violations of ordering constraints. After each trace is committed, the sub-circuit invalidates all of the memory operation ordering information associated with the trace.
摘要翻译：处理器包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组在其间具有预定义的程序顺序的活动存储器操作。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。在电路运行期间，在提交跟踪之前，给定跟踪的任何操作都不会对执行单元的架构状态产生任何影响。轨迹中的所有操作完成执行后，每个轨迹都将有资格获得承诺。该电路还包括保持对应于活动存储器操作的存储器操作排序信息的子电路。子电路检测到排序限制的违规。在每个跟踪提交之后，子电路使与跟踪相关联的所有存储器操作排序信息无效。

8. 发明授权

US08010745B1 Rolling back a speculative update of a non-modifiable cache line 有权
标题翻译：回滚不可修改的缓存行的推测更新
公开(公告)号：US08010745B1
公开(公告)日：2011-08-30
申请号：US12030859
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/3808 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。当内存操作尝试更新可能未更新的高速缓存行时，该电路会尝试升级缓存行。如果失败，则会生成一个回滚请求，指示涉及的跟踪。与指示轨迹相关联的检查点位置与与所有较年轻轨迹相关联的那些位置被覆盖。

9. 发明授权

US07779307B1 Memory ordering queue tightly coupled with a versioning cache circuit 有权
标题翻译：存储器排序队列与版本缓存电路紧密耦合
公开(公告)号：US07779307B1
公开(公告)日：2010-08-17
申请号：US12030857
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. There is a one-to-one correspondence between checkpoint entries and memory operation ordering entries. Each checkpoint entry refers to a checkpoint location. Rollback requests cause the circuit to overwrite checkpoint entries associated with the corresponding trace.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。检查点条目和内存操作顺序条目之间存在一一对应关系。每个检查点条目指的是检查点位置。回滚请求导致电路覆盖与相应跟踪相关联的检查点条目。

10. 发明授权

US08370576B1 Cache rollback acceleration via a bank based versioning cache ciruit 有权
标题翻译：通过基于银行的版本缓存缓存来缓存回滚加速
公开(公告)号：US08370576B1
公开(公告)日：2013-02-05
申请号：US12030858
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F12/00
CPC分类号： G06F12/0855 , G06F9/3863 , Y02D10/13
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. At least some of the active memory operations access the memory in an execution order that is different from the program order. The circuit includes a first memory that caches data accessed by the memory operations. This memory is partitioned into N banks. Checkpoint entries, which are stored in a second memory also partitioned into N banks, are associated with each trace. Each entry refers to a checkpoint location in the first memory. A sub-circuit receives rollback requests and responds by overwriting checkpoint locations. Each of the N memory units consisting of a bank in the first memory and the corresponding bank in the second memory may be rolled back independently and concurrently with other memory units.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。该电路包括缓存由存储器操作访问的数据的第一存储器。该内存被划分为N个存储区。存储在也划分为N个存储区的第二个存储器中的检查点条目与每个跟踪相关联。每个条目是指第一个内存中的检查点位置。子电路接收回滚请求并通过覆盖检查点位置进行响应。由第一存储器中的存储体和第二存储器中的相应存储体组成的N个存储器单元中的每一个可以独立地并与其它存储器单元一起回滚。

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