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1. 发明授权

US06284608B1 Method for making accumulation mode N-channel SOI 有权
标题翻译：用于制作累积模式N沟道SOI的方法
公开(公告)号：US06284608B1
公开(公告)日：2001-09-04
申请号：US09496245
申请日：2000-02-01
申请人： Zoran Krivakapic , Srinath Krishnan , Witold Maszara
发明人： Zoran Krivakapic , Srinath Krishnan , Witold Maszara
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78696
摘要： A method of manufacturing an accumulation mode n-channel Silicon On Insulator (SOI) transistor includes forming an intrinsic silicon body region implanted with two deep Boron and one shallow Phosphorous implants; forming source/drain regions each implanted with Arsenic; and forming p-type regions adjacent each of the source and drain regions and disposed along the transistor channel. The SOI transistor has a higher transconductance than known SOI devices.
摘要翻译：一种制造堆积模式n沟道绝缘体（SOI）晶体管的方法包括：形成植入两个深硼和一个浅磷植入物的本征硅体区域; 形成每个植入砷的源/漏区; 以及在所述源极和漏极区域中的每一个附近形成并且沿着所述晶体管沟道布置的p型区域。 SOI晶体管具有比已知SOI器件更高的跨导。

2. 发明授权

US06274915B1 Method of improving MOS device performance by controlling degree of depletion in the gate electrode 有权
标题翻译：通过控制栅电极的耗尽程度来提高MOS器件性能的方法
公开(公告)号：US06274915B1
公开(公告)日：2001-08-14
申请号：US09225646
申请日：1999-01-05
申请人： Srinath Krishnan , Ming-Yin Hao , David Bang , Witold Maszara
发明人： Srinath Krishnan , Ming-Yin Hao , David Bang , Witold Maszara
IPC分类号： H01L2976
CPC分类号： H01L29/4916 , H01L29/1033
摘要： A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1×1019 and 5×1019 atoms/cm3.
摘要翻译： MOS晶体管的设计故意使用多晶硅栅电极中的耗尽来改善电路性能。常规的晶体管设计旨在最小化多晶硅栅电极的耗尽以增加驱动电流。根据本发明的实施例，大于常规电平的栅电极的适当耗尽量同时提供期望的驱动电流同时最小化电路延迟。根据另一方面，通过调整沟道区域中的掺杂水平来改善电路性能，以将阈值电压维持在与多晶硅栅电极中的最小耗尽所达到的阈值电压相同的水平。还提供了一种制造包括具有增加的耗尽的多晶硅栅电极的MOS器件的方法。使用自对准掺杂工艺，其中多晶硅栅极，源极区域和漏极区域被同时注入到掺杂剂浓度为1×1019至5×1019原子/ cm3之间。

3. 发明授权

US06492209B1 Selectively thin silicon film for creating fully and partially depleted SOI on same wafer 失效
标题翻译：选择性薄的硅膜，用于在同一晶圆上产生完全和部分耗尽的SOI
公开(公告)号：US06492209B1
公开(公告)日：2002-12-10
申请号：US09607629
申请日：2000-06-30
申请人： Srinath Krishnan , Matthew Buynoski , Witold Maszara
发明人： Srinath Krishnan , Matthew Buynoski , Witold Maszara
IPC分类号： H01L21302
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. At least one trench is etched into a bulk semiconductor wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.
摘要翻译：一种用于在同一半导体晶片上提供部分耗尽和完全耗尽的晶体管器件的方法。至少一个沟槽被蚀刻到体半导体晶片中。然后将晶片填充绝缘材料并抛光至半导体晶片的表面水平以形成大致平坦的表面。提供具有基底层和绝缘层的处理晶片。半导体晶片的平面被接合到处理晶片的绝缘层上。半导体晶片的沟槽填充区域形成第一厚度的区域，并且半导体晶片的其余区域形成第二厚度的区域。然后可以在第一厚度的区域中形成完全耗尽的晶体管器件，并且可以在第二厚度的区域中形成部分耗尽的晶体管器件。

4. 发明授权

US06399452B1 Method of fabricating transistors with low thermal budget 有权
标题翻译：低热预算制造晶体管的方法
公开(公告)号：US06399452B1
公开(公告)日：2002-06-04
申请号：US09612200
申请日：2000-07-08
申请人： Srinath Krishnan , Witold Maszara
发明人： Srinath Krishnan , Witold Maszara
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/324
摘要： A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by ion implantation. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, second amorphous regions and second inactive dopant regions are created in the substrate by ion implantation. Dopants in the first and second inactive dopant regions are then activated using a low temperature annealing process to create source/drain regions and source/drain extension regions. The aforementioned process simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.
摘要翻译：通过首先在半导体衬底上形成栅极来制造低热预算晶体管。然后通过离子注入在衬底中产生第一非晶区域和第一非活性掺杂剂区域。对准随后的注入步骤的侧壁间隔件邻近门形成。此后，通过离子注入在衬底中产生第二非晶区域和第二非活性掺杂剂区域。然后使用低温退火工艺激活第一和第二非活性掺杂剂区域中的掺杂剂，以产生源极/漏极区域和源极/漏极延伸区域。上述过程通过分配去除侧壁间隔物的要求简化了低热预算晶体管的制造。

5. 发明申请

US20050048743A1 Method of growing as a channel region to reduce source/drain junction capicitance 有权
标题翻译：作为渠道区域生长以减少源/汇交汇率资本的方法
公开(公告)号：US20050048743A1
公开(公告)日：2005-03-03
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
发明人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

6. 发明申请

US20090294896A1 SHALLOW TRENCH ISOLATION PROCESS UTILIZING DIFFERENTIAL LINERS 有权
标题翻译：使用差异衬线的浅层分离工艺
公开(公告)号：US20090294896A1
公开(公告)日：2009-12-03
申请号：US12538008
申请日：2009-08-07
申请人： Srinath Krishnan
发明人： Srinath Krishnan
IPC分类号： H01L29/06
CPC分类号： H01L21/823807 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L29/7846
摘要： A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.
摘要翻译：集成电路（IC）的制造方法可以利用浅沟槽隔离（STI）技术。浅沟槽隔离技术可用于IC工艺。用于沟槽的单独衬垫用于NMOS和PMOS区域。衬垫可以在衬底中引起应变。

7. 发明授权

US06713819B1 SOI MOSFET having amorphized source drain and method of fabrication 失效
标题翻译：具有非晶化源极漏极和制造方法的SOI MOSFET
公开(公告)号：US06713819B1
公开(公告)日：2004-03-30
申请号：US10118364
申请日：2002-04-08
申请人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
发明人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
IPC分类号： H01L2976
CPC分类号： H01L29/78609 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
摘要翻译：一种以绝缘体半导体形式形成的集成电路。集成电路包括设置在绝缘层上的半导体材料层，其中设置在基板上的绝缘层。提供第一和第二MOSFET，使得第一MOSFET的源极和漏极中的一个被设置为邻近第二MOSFET的源极和漏极之一。在半导体材料层中形成非晶区域并从半导体材料层的上表面延伸到隔离层。非晶区域形成在第一MOSFET的源极和漏极之一的结晶部分和第二MOSFET的源极和漏极之一的结晶部分之间。

8. 发明授权

US06589823B1 Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug 失效
标题翻译：具有背面接触插头的绝缘体上硅（SOI）静电放电（ESD）保护装置
公开(公告)号：US06589823B1
公开(公告)日：2003-07-08
申请号：US09792138
申请日：2001-02-22
申请人： Stephen G. Beebe , Srinath Krishnan , Zoran Krivokapic
发明人： Stephen G. Beebe , Srinath Krishnan , Zoran Krivokapic
IPC分类号： H01L2100
CPC分类号： H01L27/0255
摘要： An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.
摘要翻译：一种用于绝缘体上硅（SOI）集成电路的静电放电（ESD）保护装置，其具有设置在其上的掩埋氧化物层的硅衬底和设置在具有由隔离沟槽限定的有源区的掩埋氧化物层上的有源层。 ESD保护器件形成在SOI集成电路上，并且具有形成在有源区域之一内的阳极和阴极，并且分别耦合到第一和第二节点; 以及与所述阳极或阴极中的至少一个相邻并与其接触的背面接触插塞，所述背面接触插塞穿过所述掩埋氧化物层以热耦合所述有源区域和所述衬底之一。

9. 发明授权

US06465847B1 Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions 失效
标题翻译：绝缘体上半导体器件（SOI）器件，具有超导源极/漏极结
公开(公告)号：US06465847B1
公开(公告)日：2002-10-15
申请号：US09878614
申请日：2001-06-11
申请人： Srinath Krishnan , Witold P. Maszara
发明人： Srinath Krishnan , Witold P. Maszara
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665 , H01L29/78621
摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes a semiconductor substrate layer; an insulator layer disposed on the substrate layer; a semiconductor active region disposed on the insulator layer, the active region including a source, a drain, and a body disposed therebetween, at least one of the source and the drain forming a hyperabrupt junction with the body; and a gate disposed on the body such that the gate, source, drain and body are operatively arranged to form a transistor. The at least one of the source and drain forming the hyperabrupt junction with the body includes a silicide region. The silicide region has a generally vertical interface, which is laterally spaced apart from the hyperabrupt junction by about 60 Å to about 150 Å.
摘要翻译：绝缘体上半导体（SOI）器件。 SOI器件包括半导体衬底层; 设置在所述基板层上的绝缘体层; 设置在所述绝缘体层上的半导体有源区，所述有源区包括源极，漏极和设置在其间的主体，所述源极和漏极中的至少一个与所述主体形成超级连接; 以及设置在所述主体上的门，使得所述栅极，源极，漏极和主体被可操作地布置以形成晶体管。与主体形成超破裂结的源极和漏极中的至少一个包括硅化物区域。硅化物区域具有大致垂直的界面，其与超破裂结交叉横向间隔约60埃至约150埃。

10. 发明授权

US06429054B1 Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions 失效
标题翻译：制造绝缘体上半导体（SOI）器件的方法，其具有过度的源极/漏极结
公开(公告)号：US06429054B1
公开(公告)日：2002-08-06
申请号：US09878791
申请日：2001-06-11
申请人： Srinath Krishnan , Witold P. Maszara
发明人： Srinath Krishnan , Witold P. Maszara
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/26513 , H01L29/458 , H01L29/665 , H01L29/78621
摘要： A method of forming a semiconductor-on-insulator (SOI) device. The method includes providing an SOI wafer having an active layer, a substrate and a buried insulator layer therebetween; defining an active region in the active layer; forming a source, a drain and body in the active region, the source and the drain forming respective hyperabrupt junctions with the body, the hyperabrupt junctions being formed by an SPE process which includes amorphizing the at least one of the source and the drain, implanting dopant ion species and recrystalizing at temperature of less than 700° C.; forming a gate disposed on the body such that the source, drain, body and gate are operatively arranged to form a transistor; and forming a silicide region in each of the source and the drain, the silicide regions being spaced from the respective hyperabrupt junctions by a lateral distance of less than about 100 Å.
摘要翻译：一种形成绝缘体上半导体（SOI）器件的方法。该方法包括提供具有有源层，衬底和其间的掩埋绝缘体层的SOI晶片; 在有源层中限定有源区; 在有源区域中形成源极，漏极和主体，源极和漏极与主体形成相应的过度连接点，超破裂结由SPE工艺形成，其包括将源极和漏极中的至少一个非晶化，植入掺杂剂离子种类，并在低于700℃的温度下重结晶; 形成设置在所述主体上的栅极，使得所述源极，漏极，主体和栅极可操作地布置以形成晶体管; 并且在源极和漏极的每一个中形成硅化物区域，硅化物区域与相应的超破裂接合部分间隔小于约100A的横向距离。

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