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1. 发明授权

US07471131B2 Delay locked loop with common counter and method thereof 有权
标题翻译：延迟锁定环与公共计数器及其方法
公开(公告)号：US07471131B2
公开(公告)日：2008-12-30
申请号：US11468359
申请日：2006-08-30
申请人： Zhongding Liu , Zhen-Yu Song , Ken-Ming Li , Joe Bi , Sally Qu
发明人： Zhongding Liu , Zhen-Yu Song , Ken-Ming Li , Joe Bi , Sally Qu
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.
摘要翻译：延迟锁定环路电路，用于延迟输入时钟锁定延迟时钟。延迟锁定环包括用于将输入时钟的频率除以数字N的分频器，以获得分频时钟;多个延迟分量，用于延迟输入时钟以根据相位而产生具有不同相位的多个延迟时钟计数值，耦合到用于检测最终延迟时钟和输入时钟之间的相位的最终延迟分量的相位检测器，以及耦合到相位检测器和分频器的计数器，用于根据相位转换产生计数值在最后的延迟时钟和输入时钟之间。

2. 发明申请

US20070046348A1 DELAY LOCKED LOOP WITH COMMON COUNTER AND METHOD THEREOF 有权
标题翻译：延迟锁定循环与通用计数器及其方法
公开(公告)号：US20070046348A1
公开(公告)日：2007-03-01
申请号：US11468359
申请日：2006-08-30
申请人： Zhongding Liu , Zhen-Yu Song , Ken-Ming Li , Joe Bi , Sally Qu
发明人： Zhongding Liu , Zhen-Yu Song , Ken-Ming Li , Joe Bi , Sally Qu
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.
摘要翻译：延迟锁定环路电路，用于延迟输入时钟锁定延迟时钟。延迟锁定环包括用于将输入时钟的频率除以数字N的分频器，以获得分频时钟;多个延迟分量，用于延迟输入时钟以根据相位而产生具有不同相位的多个延迟时钟计数值，耦合到用于检测最终延迟时钟和输入时钟之间的相位的最终延迟分量的相位检测器，以及耦合到相位检测器和分频器的计数器，用于根据相位转换产生计数值在最后的延迟时钟和输入时钟之间。

3. 发明授权

US07154294B2 Comparators capable of output offset calibration 有权
公开(公告)号：US07154294B2
公开(公告)日：2006-12-26
申请号：US11063762
申请日：2005-02-23
申请人： Zhongding Liu , Joe Bi , Ken-Ming Li , Gray Pan , Gary Yang
发明人： Zhongding Liu , Joe Bi , Ken-Ming Li , Gray Pan , Gary Yang
IPC分类号： H03K17/16
CPC分类号： H03K5/249 , H03K5/2481
摘要： Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled to the differential logic signals at the output terminals of the MCML circuit to amplify the differential logic signal and generating a comparison resulting signal. By adjusting the digital calibration codes applied to the calibration unit, current on the output terminals can be adjusted, such that output offsets at the output terminals of the MCML circuit 10 can be eliminated.

4. 发明申请

US20060186928A1 Comparators capable of output offset calibration 有权
标题翻译：能够输出偏移校准的比较器
公开(公告)号：US20060186928A1
公开(公告)日：2006-08-24
申请号：US11063762
申请日：2005-02-23
申请人： Zhongding Liu , Joe Bi , Ken-Ming Li , Gray Pan , Gary Yang
发明人： Zhongding Liu , Joe Bi , Ken-Ming Li , Gray Pan , Gary Yang
IPC分类号： H03K5/22
CPC分类号： H03K5/249 , H03K5/2481
摘要： Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled to the differential logic signals at the output terminals of the MCML circuit to amplify the differential logic signal and generating a comparison resulting signal. By adjusting the digital calibration codes applied to the calibration unit, current on the output terminals can be adjusted, such that output offsets at the output terminals of the MCML circuit 10 can be eliminated.
摘要翻译：比较器输出偏移校准。 MOS电流模式逻辑（MCML）电路接收输入信号并在其输出端产生差分逻辑信号，并且包括耦合到输出端的校准单元，根据数字校准代码来校准输出端的输出偏移。输出级耦合到MCML电路的输出端的差分逻辑信号，以放大差分逻辑信号并产生比较结果信号。通过调整应用于校准单元的数字校准代码，可以调节输出端子上的电流，从而可以消除MCML电路10的输出端子处的输出偏移。

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