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1. 发明申请

US20110006371A1 INDUCING STRESS IN CMOS DEVICE 有权
标题翻译：在CMOS器件中产生应力
公开(公告)号：US20110006371A1
公开(公告)日：2011-01-13
申请号：US12500107
申请日：2009-07-09
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and forming a contact in the opening.
摘要翻译：本发明的第一方面提供一种形成半导体器件的方法，所述方法包括：提供互补金属氧化物半导体（CMOS）器件，其包括：硅衬底层; 二氧化硅层; 和具有第一凹陷源极/漏极沟槽的n型场效应晶体管（NFET）栅极和具有第二凹陷源极/漏极沟槽的p型场效应晶体管（PFET）栅极，所述NFET栅极和PFET栅极位于二氧化硅层; 在第一凹陷源极/漏极沟槽和第二凹陷源极/漏极沟槽中沉积氮化物应力衬垫; 在氮化物应力衬垫上沉积氧化物层; 将CMOS器件放置在处理晶片上，其中氧化物层最靠近处理晶片; 去除硅衬底层; 蚀刻所述二氧化硅层以形成邻接所述源/漏区的一部分的开口，所述源极/漏极区邻接所述第一凹陷源极/漏极沟槽或所述第二凹陷源极/漏极沟槽中的一个; 并在开口中形成接触。

2. 发明授权

US08169026B2 Stress-induced CMOS device 有权
标题翻译：应力感应CMOS器件
公开(公告)号：US08169026B2
公开(公告)日：2012-05-01
申请号：US13242380
申请日：2011-09-23
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
摘要翻译：一种半导体器件，包括：二氧化硅层; n型场效应晶体管（NFET），其包括至少一个凹陷源极/漏极沟槽，并位于所述二氧化硅层的一部分上方; p型场效应晶体管（PFET），其包括至少一个凹陷源极/漏极沟槽并且位于所述二氧化硅层的一部分上方; 在NFET和PFET上的氮化物应力衬垫，氮化物应力衬垫填充NFET的至少一个凹陷源极/漏极沟槽和PFET的至少一个凹陷源极/漏极沟槽; 以及形成在所述二氧化硅层中的第一接触件，所述第一接触件邻接所述NFET或PFET之一。

3. 发明授权

US08105887B2 Inducing stress in CMOS device 有权
标题翻译：在CMOS器件中引起应力
公开(公告)号：US08105887B2
公开(公告)日：2012-01-31
申请号：US12500107
申请日：2009-07-09
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and forming a contact in the opening.
摘要翻译：本发明的第一方面提供一种形成半导体器件的方法，所述方法包括：提供互补金属氧化物半导体（CMOS）器件，其包括：硅衬底层; 二氧化硅层; 和具有第一凹陷源极/漏极沟槽的n型场效应晶体管（NFET）栅极和具有第二凹陷源极/漏极沟槽的p型场效应晶体管（PFET）栅极，所述NFET栅极和PFET栅极位于二氧化硅层; 在第一凹陷源极/漏极沟槽和第二凹陷源极/漏极沟槽中沉积氮化物应力衬垫; 在氮化物应力衬垫上沉积氧化物层; 将CMOS器件放置在处理晶片上，其中氧化物层最靠近处理晶片; 去除硅衬底层; 蚀刻所述二氧化硅层以形成邻接所述源/漏区的一部分的开口，所述源极/漏极区邻接所述第一凹陷源极/漏极沟槽或所述第二凹陷源极/漏极沟槽中的一个; 并在开口中形成接触。

4. 发明申请

US20120007190A1 STRESS-INDUCED CMOS DEVICE 有权
标题翻译：应力诱导CMOS器件
公开(公告)号：US20120007190A1
公开(公告)日：2012-01-12
申请号：US13242380
申请日：2011-09-23
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
摘要翻译：一种半导体器件，包括：二氧化硅层; n型场效应晶体管（NFET），其包括至少一个凹陷源极/漏极沟槽，并位于所述二氧化硅层的一部分上方; p型场效应晶体管（PFET），其包括至少一个凹陷源极/漏极沟槽并且位于所述二氧化硅层的一部分上方; 在NFET和PFET上的氮化物应力衬垫，氮化物应力衬垫填充NFET的至少一个凹陷源极/漏极沟槽和PFET的至少一个凹陷源极/漏极沟槽; 以及形成在所述二氧化硅层中的第一接触件，所述第一接触件邻接所述NFET或PFET之一。

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