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1. 发明授权

US07378289B1 Method for forming photomask having test patterns in blading areas 有权
标题翻译：用于形成具有在叶片区域中的测试图案的光掩模的方法
公开(公告)号：US07378289B1
公开(公告)日：2008-05-27
申请号：US11100144
申请日：2005-04-05
申请人： Zhijian Ma , Pao-Lu Huang , Pauli Hsueh , Jeong Choi
发明人： Zhijian Ma , Pao-Lu Huang , Pauli Hsueh , Jeong Choi
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： H01L22/34
摘要： A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a test pattern for a different process step is formed in a blading area of the photomask. Also, a method for forming test structures is disclosed in which the photomask is exposed to transfer the test pattern to a semiconductor substrate. The process step that is associated with the test pattern is then performed, forming a test structure on the semiconductor substrate. By utilizing blading areas of photomasks and including test patterns for different process steps on the same photomask, more test structures can be obtained, without the need to generate additional photomasks for testing purposes.
摘要翻译：公开了一种光掩模和用于形成光掩模的方法，其中限定用于半导体制造工艺的工艺步骤的特征的管芯区域形成在光掩模上，并且在光掩模的叶片区域中形成用于不同工艺步骤的测试图案。此外，公开了一种用于形成测试结构的方法，其中曝光光掩模以将测试图案转移到半导体衬底。然后执行与测试图案相关联的工艺步骤，在半导体衬底上形成测试结构。通过在同一光掩模上利用光掩模的叶片区域和不同工艺步骤的测试图案，可以获得更多的测试结构，而无需生成额外的光掩模用于测试目的。

2. 发明申请

US20070234125A1 Logic soft error rate prediction and improvement 有权
标题翻译：逻辑软错误率预测与改进
公开(公告)号：US20070234125A1
公开(公告)日：2007-10-04
申请号：US11395119
申请日：2006-03-31
申请人： Chuen-Der Lien , Pao-Lu Huang
发明人： Chuen-Der Lien , Pao-Lu Huang
IPC分类号： G06F11/00
CPC分类号： G01R31/31816
摘要： A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.
摘要翻译：一种用于估计集成电路的软错误率的过程和系统。该过程涉及确定存储在集成电路上的每个逻辑节点上的表面积和电荷。然后使用响应曲线来使用存储在逻辑节点上的电荷来估计逻辑节点的软错误率。不同技术和产品的集成电路存在不同的响应曲线。最后，可以使用每个逻辑节点的软错误率来估计集成电路的软错误率。

3. 发明申请

US20060227649A1 Dual port memory cell with reduced coupling capacitance and small cell size 有权
标题翻译：具有减小的耦合电容和小单元尺寸的双端口存储单元
公开(公告)号：US20060227649A1
公开(公告)日：2006-10-12
申请号：US11403370
申请日：2006-04-12
申请人： Chuen-Der Lien , Pao-Lu Huang
发明人： Chuen-Der Lien , Pao-Lu Huang
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/02 , G11C7/1075 , G11C7/18
摘要： A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.
摘要翻译：一种双端口或多端口存储器件，包括与第一端口相关联的与第二端口相关联的第二组位线的第一组位线，其中位线布置在不同的金属化层中并且水平分开以减少一个或两个与位线相关的杂散和耦合电容。在一个示例性实施例中，来自更接近另一（或另一）端口的位线的每个端口的位线被布置在不同的金属化层中以减小它们之间的耦合电容。一个或多个另外的实施例可以包括水平位于位线和用于位线的金属到衬底触点之间的V SS或V DD线，可以形成为相反的存储器件的角落，以进一步降低电容。

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