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1. 发明申请

US20140160707A1 NON-UNIFORM SUBSTRATE STACKUP 有权
标题翻译：非均匀基板堆叠
公开(公告)号：US20140160707A1
公开(公告)日：2014-06-12
申请号：US13707113
申请日：2012-12-06
申请人： Zhichao Zhang , Tao Wu , Zhiguo Qian , Kemal Aygun
发明人： Zhichao Zhang , Tao Wu , Zhiguo Qian , Kemal Aygun
IPC分类号： H05K1/18 , H05K3/10 , H05K1/02
CPC分类号： H05K1/0298 , H01L21/4846 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/0216 , H05K2201/0191 , H05K2201/0352 , H05K2201/09736 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , Y10T29/49155 , H01L2924/00
摘要： Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.
摘要翻译：本文描述的一些实施例包括形成这种装置的装置和方法。一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。第一和第二迹线可以具有不同的厚度。描述包括附加装置和方法的其他实施例。

2. 发明申请

US20140268614A1 COUPLED VIAS FOR CHANNEL CROSS-TALK REDUCTION 审中-公开
标题翻译：用于通道交叉减少的联合VIAS
公开(公告)号：US20140268614A1
公开(公告)日：2014-09-18
申请号：US13802011
申请日：2013-03-13
申请人： Zhichao ZHANG , Zhiguo Qian , Tolga Memioglu , Kemal Aygun
发明人： Zhichao ZHANG , Zhiguo Qian , Tolga Memioglu , Kemal Aygun
IPC分类号： H05K1/02 , H05K1/18 , H01L21/768
CPC分类号： H01L21/768 , H01L23/49822 , H01L23/50 , H01L2224/16235 , H01L2924/15311 , H05K1/0228 , H05K1/0251 , H05K1/0298
摘要： Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.
摘要翻译：电容耦合的垂直转换可以配置有期望量的互电容，以至少部分地消除整个信道串扰（例如，FEXT）减少的串扰。在实施例中，相邻垂直转变的电容耦合是通过垂直转换内的重叠金属表面实现的。在实施例中，一个或多个重叠金属表面是从垂直过渡延伸的通孔，通孔焊盘或金属短截线特征。在实施例中，利用具有重叠垂直转换的信号路径来实现多于一个受害者 - 攻击者对的串扰减少和/或实现多于两个侵略者的串扰减少。在实施例中，在封装衬底，插入器或印刷电路板中实现电容耦合的垂直转变。

3. 发明授权

US09622339B2 Routing design for high speed input/output links 有权
公开(公告)号：US09622339B2
公开(公告)日：2017-04-11
申请号：US13610663
申请日：2012-09-11
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H05K1/02 , H05K3/46 , H05K1/11
CPC分类号： H05K1/0228 , H05K1/0219 , H05K1/0243 , H05K1/113 , H05K3/4644 , H05K2201/09336 , H05K2201/09672 , H05K2201/09709 , H05K2201/09727 , Y10T29/49155
摘要： Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

4. 发明申请

US20140117552A1 X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS 有权
标题翻译：用于DENSE多芯片封装互连的X线路由
公开(公告)号：US20140117552A1
公开(公告)日：2014-05-01
申请号：US13665706
申请日：2012-10-31
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H01L23/52
CPC分类号： H01L23/53228 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/105 , H01L2224/16225 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.
摘要翻译：描述了用于密集多芯片封装互连的X线路由布置。在一个示例中，电子信号路由结构包括基板。多个导电迹线层设置在衬底上。第一对接地迹线设置在多个导电迹线层中的第一层中。信号迹线设置在多层导电迹线的第二层中，位于第一层下方。第二对接地迹线设置在多层导电迹线的第三层中，位于第一层下方。第一和第二对接地迹线和信号迹线从横截面的角度提供X图案布线。

5. 发明申请

US20190229056A1 BRIDGE DIE DESIGN FOR HIGH BANDWIDTH MEMORY INTERFACE 审中-公开
公开(公告)号：US20190229056A1
公开(公告)日：2019-07-25
申请号：US16305758
申请日：2016-06-30
申请人： Zhiguo Qian , Kemal Aygun , Dae-Woo Kim , Jackie C. Preciado
发明人： Zhiguo Qian , Kemal Aygun , Dae-Woo Kim , Jackie C. Preciado
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00
摘要： A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

6. 发明授权

US09240377B2 X-line routing for dense multi-chip-package interconnects 有权
公开(公告)号：US09240377B2
公开(公告)日：2016-01-19
申请号：US14579073
申请日：2014-12-22
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/532 , H01L23/538 , H01L23/528 , H01L25/10 , H01L23/498
CPC分类号： H01L23/53228 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/105 , H01L2224/16225 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

7. 发明申请

US20140071646A1 ROUTING DESIGN FOR HIGH SPEED INPUT/OUTPUT LINKS 有权
标题翻译：高速输入/输出链路的路由设计
公开(公告)号：US20140071646A1
公开(公告)日：2014-03-13
申请号：US13610663
申请日：2012-09-11
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H05K1/02 , H05K3/46
CPC分类号： H05K1/0228 , H05K1/0219 , H05K1/0243 , H05K1/113 , H05K3/4644 , H05K2201/09336 , H05K2201/09672 , H05K2201/09709 , H05K2201/09727 , Y10T29/49155
摘要： Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.
摘要翻译：某些实施例涉及路由结构及其形成。在一个实施例中，路由结构包括包括第一层的第一区域，第一层包括交替的信号迹线和由电介质隔开的接地迹线。第一区域还包括第二层，其包括由电介质隔开的交替信号迹线和接地迹线，其中位于第一层接地迹线上方的第二层信号，以及位于第一层信号迹线上的第二层接地迹线。第一区域还可以包括交替信号和接地迹线的附加层。第一区域也可以形成有具有大于信号迹线的宽度的接地迹线。路由结构还可以包括包括跟踪耦合到其上的焊盘的第二区域。描述和要求保护其他实施例。

8. 发明申请

US20150102477A1 X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS 审中-公开
标题翻译：用于DENSE多芯片封装互连的X线路由
公开(公告)号：US20150102477A1
公开(公告)日：2015-04-16
申请号：US14579073
申请日：2014-12-22
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H01L23/532 , H01L25/10 , H01L23/498 , H01L23/528
CPC分类号： H01L23/53228 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/105 , H01L2224/16225 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.
摘要翻译：描述了用于密集多芯片封装互连的X线路由布置。在一个示例中，电子信号路由结构包括基板。多个导电迹线层设置在衬底上。第一对接地迹线设置在多个导电迹线层中的第一层中。信号迹线设置在多层导电迹线的第二层中，位于第一层下方。第二对接地迹线设置在多层导电迹线的第三层中，位于第一层下方。第一和第二对接地迹线和信号迹线从横截面的角度提供X图案布线。

9. 发明授权

US08946900B2 X-line routing for dense multi-chip-package interconnects 有权
标题翻译：用于密集多芯片封装互连的X线路由
公开(公告)号：US08946900B2
公开(公告)日：2015-02-03
申请号：US13665706
申请日：2012-10-31
申请人： Zhiguo Qian , Kemal Aygun
发明人： Zhiguo Qian , Kemal Aygun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53228 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/528 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/105 , H01L2224/16225 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.
摘要翻译：描述了用于密集多芯片封装互连的X线路由布置。在一个示例中，电子信号路由结构包括基板。多个导电迹线层设置在衬底上。第一对接地迹线设置在多个导电迹线层中的第一层中。信号迹线设置在多层导电迹线的第二层中，位于第一层下方。第二对接地迹线设置在多层导电迹线的第三层中，位于第一层下方。第一和第二对接地迹线和信号迹线从横截面的角度提供X图案布线。

10. 发明授权

US09548734B1 Smart impedance matching for high-speed I/O 有权
标题翻译：智能阻抗匹配用于高速I / O
公开(公告)号：US09548734B1
公开(公告)日：2017-01-17
申请号：US14998090
申请日：2015-12-26
申请人： Hongjiang Song , Yan W. Song , Zhiguo Qian , Zhichao Zhang
发明人： Hongjiang Song , Yan W. Song , Zhiguo Qian , Zhichao Zhang
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0005 , H03K19/017545
摘要： Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.
摘要翻译：实施例通常涉及用于高速I / O的智能阻抗匹配。在一些实施例中，电路包括阻抗感测块; 有限状态机为驱动器提供阻抗调谐; 和控制块，控制块提供反馈回路来检查和调谐驱动器的阻抗。阻抗感测块用于对驱动器的输出电压进行采样，以确定驱动器的阻抗是否大于或小于通道的阻抗; 并且有限状态机基于确定驾驶员的阻抗是否大于或小于通道的阻抗来产生信号以减小或增加驾驶员的阻抗。

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