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    • 1. 发明申请
    • Single crystal growth method for vertical high temperature and high pressure group III-V compound
    • 用于垂直高温高压组III-V化合物的单晶生长方法
    • US20120260848A1
    • 2012-10-18
    • US13443965
    • 2012-04-11
    • Zhi HeXiao-Yu Hu
    • Zhi HeXiao-Yu Hu
    • C30B11/12
    • C30B29/40C30B11/12
    • The invention discloses a single crystal growth method for a vertical high temperature and high pressure group III-V compound. A vertical high temperature and high pressure stove is capable of providing a group III element fusion zone with a temperature equal to or greater than that of a composition melting point and providing a group V element provision zone below the group III element fusion zone. The stove provides steam to the group III element fusion zone and the group V element provision zone at a temperature greater than evaporation temperature. The compound synthesis of a group III element and a group V element is completed in the group III element fusion zone, and an in-situ growth of single crystal is completed in the group III element fusion zone, thereby preventing the growth of the rich group III element and increasing the single crystal process efficiency.
    • 本发明公开了一种用于垂直高温高压III-V族化合物的单晶生长方法。 垂直高温高压炉能够提供等于或大于成分熔点温度的III族元素熔融区,并提供在III族元素熔融区下方的V族元素提供区。 炉子在大于蒸发温度的温度下,向III族元素熔融区和V族元素供应区提供蒸汽。 III族元素和V族元素的复合合成在III族元素熔融区完成,在III族元素熔融区中完成单晶的原位生长,从而防止富集的生长 III元素,提高单晶工艺效率。
    • 2. 发明授权
    • Enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication
    • 增强型III-V族高电子迁移率晶体管(HEMT)及其制造方法
    • US08604486B2
    • 2013-12-10
    • US13157562
    • 2011-06-10
    • Zhi He
    • Zhi He
    • H01L31/0256
    • H01L29/7786H01L29/1066H01L29/2003H01L29/66462
    • According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
    • 根据一个公开的实施例,增强型高电子迁移率晶体管(HEMT)包括异质结,其包括位于III-V族半导体本体上的III-V族阻挡层,以及形成在III-V族阻挡层上的栅极结构 并且包括P型III-V族栅极层。 P型III-V族栅极层防止在栅极结构下形成二维电子气(2°)。 制造这种增强型HEMT的方法的一个实施例包括提供衬底,在衬底上形成III-V族半导体体,在III-V族半导体体上形成III-V族阻挡层,并形成栅极 结构包括III-V族阻挡层上的P型III-V族栅极层。
    • 6. 发明申请
    • Gated AlGaN/GaN Schottky Device
    • 门控AlGaN / GaN肖特基器件
    • US20130001648A1
    • 2013-01-03
    • US13609746
    • 2012-09-11
    • Zhi He
    • Zhi He
    • H01L29/205H01L29/872
    • H01L29/872H01L29/2003H01L29/205H01L29/402
    • Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode.
    • 已经公开了使用III族氮化物异质结的半导体器件的一些示例性实施例以及产生适用于高电压电路设计的这种半导体器件的新型肖特基结构和相关方法。 一个示例性结构包括包含第一III族氮化物材料的第一层,包含与所述第一层形成异质结的第二III族氮化物材料的第二层,以在所述第一层内产生二维电子气(2DEG),阳极包括 至少在所述第二层的表面上形成肖特基接触的第一金属部分,在所述第二层的所述表面上形成欧姆接触的阴极,在所述第二层的所述表面上的场介电层,用于隔离所述阳极和所述阴极 以及在所述第二层的所述表面上并与所述阳极接触的绝缘材料。
    • 8. 发明申请
    • Semiconductor structure including a field modulation body and method for fabricating same
    • 包括场调制体的半导体结构及其制造方法
    • US20110049569A1
    • 2011-03-03
    • US12584293
    • 2009-09-02
    • Zhi He
    • Zhi He
    • H01L29/80H01L21/335
    • H01L29/402H01L29/2003H01L29/4238H01L29/66219H01L29/66462H01L29/7787H01L29/861
    • According to one embodiment, a semiconductor structure including an equipotential field modulation body comprises a trench surrounding an active region of a group III-V power device fabricated in the semiconductor structure, and the equipotential field modulation body formed in the trench and extending over a portion of the active region. The equipotential field modulation body is electrically coupled to a terminal of the group III-V power device. In one embodiment, a method for fabricating a semiconductor structure including an equipotential field modulation body comprises fabricating a trench surrounding an active region of the semiconductor structure, forming the equipotential field modulation body in the trench, the equipotential field modulation body extending over a portion of the active region, and electrically coupling the equipotential field modulation body to a terminal of a group III-V power device fabricated in the active region.
    • 根据一个实施例,包括等电场场调制体的半导体结构包括围绕在半导体结构中制造的III-V族功率器件的有源区的沟槽,以及形成在沟槽中并在沟槽中延伸的等电位场调制体 的活跃区域。 等电场场调制体电耦合到III-V族功率器件的端子。 在一个实施例中,制造包括等电位场调制体的半导体结构的方法包括制造围绕半导体结构的有源区的沟槽,在沟槽中形成等电场调制体,等电位场调制体延伸到 有源区,并且将等电场调制体电耦合到在有源区中制造的III-V族功率器件的端子。