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1. 发明授权

US4907147A Pipelined data processing system with register indirect addressing 失效
标题翻译：具有寄存器间接寻址的流水线数据处理系统
公开(公告)号：US4907147A
公开(公告)日：1990-03-06
申请号：US156271
申请日：1988-02-12
申请人： Yuuichi Saito , Toyohiko Yoshida
发明人： Yuuichi Saito , Toyohiko Yoshida
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3838
摘要： A system for preventing register conflict in a pipeline including a flag group memories at selected stages for storing flag groups indicating which general purpose registers are reserved by the instructions being processed at the selected stages. A flag group associated with a particular instruction is shifted with the instruction through the pipeline.
摘要翻译：一种用于防止流水线中的寄存器冲突的系统，包括在选定阶段的标志组存储器，用于存储指示哪些通用寄存器由在所选阶段处理的指令预留的标志组。与特定指令相关联的标志组通过管线与指令一起移位。

2. 发明授权

US5339446A Power supply and method for use in a computer system to confirm a save operation of the computer system and to stop a supply of power to the computer system after confirmation 失效
标题翻译：用于计算机系统的电源和方法，用于确认计算机系统的保存操作，并在确认后停止向计算机系统供电
公开(公告)号：US5339446A
公开(公告)日：1994-08-16
申请号：US062733
申请日：1993-05-18
申请人： Takuma Yamasaki , Yuuichi Saito
发明人： Takuma Yamasaki , Yuuichi Saito
IPC分类号： G06F1/24 , G06F1/26 , G06F1/30 , G06F11/00
CPC分类号： G06F1/30 , G06F1/24 , G06F1/26
摘要： A power supply for use in a computer system according to this invention has a one-chip microcomputer having a built-in A/D converter. The microcomputer, which has a communication function, performs a power off sequence for a computer system and a power off sequence for a hard disk drive built in the computer system, while communicating with the computer system. Further, the microcomputer detects the voltage and current of a chargeable battery, discriminates a low battery state, monitors a power switch, a hard disk drive switch and a reset switch, and monitors an input/output voltage.
摘要翻译：根据本发明的用于计算机系统的电源具有具有内置A / D转换器的单片微计算机。具有通信功能的微型计算机在与计算机系统通信的同时对计算机系统的内置的硬盘驱动器执行计算机系统的电源关闭顺序和停电顺序。此外，微型计算机检测可充电电池的电压和电流，识别电池电量低，监视电源开关，硬盘驱动器开关和复位开关，并监视输入/输出电压。

3. 发明授权

US5212779A System for guarantee reexecution after interruption by conditionally used store buffer if microinstruction being executed is a memory write and last microinstruction 失效
标题翻译：系统为保证重新执行中断后有条件使用的存储缓冲区，如果微指令被执行是存储器写入和最后一个微指令
公开(公告)号：US5212779A
公开(公告)日：1993-05-18
申请号：US574845
申请日：1990-08-29
申请人： Yuuichi Saito
发明人： Yuuichi Saito
IPC分类号： G06F9/28 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/28 , G06F9/3867
摘要： A data processor which is constructed such that, when writing processing of an operand to external devices is included as the last step processing of a microprogram, by moving only the writing processing to a next pipeline stage, all of external access processings during execution of the microinstruction in the other plural steps are executed in an instruction execution stage, thereby information showing the internal states such as PSW, PC, and the like can be managed in the instruction execution stage alone to facilitate exceptional processing.
摘要翻译：一种数据处理器，其被构造成使得当将操作数写入外部设备的处理被包括作为微程序的最后一步处理时，通过仅将写入处理移动到下一个流水线级，在执行期间的所有外部访问处理在指令执行阶段执行其他多个步骤中的微指令，从而可以在指令执行阶段单独地管理示出诸如PSW，PC等的内部状态的信息，以促进特殊处理。

4. 发明授权

US5509137A Store processing method in a pipelined cache memory 失效
标题翻译：流水线高速缓冲存储器中的存储处理方法
公开(公告)号：US5509137A
公开(公告)日：1996-04-16
申请号：US210106
申请日：1994-03-16
申请人： Fujio Itomitsu , Yuuichi Saito
发明人： Fujio Itomitsu , Yuuichi Saito
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0855
摘要： A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address register are transferred to the second address register through a transferring path in a write operation. Tag comparison and a data write of a result of the preceding comparison are executed in parallel in the same clock period, and thereby speed of processing is higher in the case of consecutive write operations at a write hit.
摘要翻译：高速缓冲存储器装置及其微处理器具有用于标签存储器的第一地址寄存器和用于数据存储器的第二地址寄存器，标签条目解码器和数据输入解码器。存储在第一地址寄存器中的内容的低位比特通过写入操作中的传送路径被传送到第二地址寄存器。标签比较和上述比较结果的数据写入在相同的时钟周期内并行执行，从而在写命中的连续写入操作的情况下处理速度更高。

5. 发明授权

US5301296A Microprocessor with cache memory 失效
标题翻译：具有缓存的微处理器
公开(公告)号：US5301296A
公开(公告)日：1994-04-05
申请号：US716411
申请日：1991-06-17
申请人： Atsushi Mohri , Yuuichi Saito
发明人： Atsushi Mohri , Yuuichi Saito
IPC分类号： G06F12/08 , G06F12/04 , G06F13/00
CPC分类号： G06F12/0886 , G06F12/0864
摘要： A microprocessor which has a plurality of cache memory units with plural ways, a plurality of data buses each having different bus width, and a write way control unit or an address control unit whichever capable of switching the number of ways or entries of these cache memory units in accordance with a bus mode determined by a specified data bus and accessing specific cache memory units, where by switching the number of ways or entries in accordance with the set bus mode the byte number of fetched instructions and data is brought into perfect accord with the data width (line size) of respective cache memory units during any bus mode. This in turn fully eliminates unused region of respective cache memory units to provide the improved efficiency of the use of the entire cache memory units.
摘要翻译：具有多个具有多路的高速缓冲存储器单元的微处理器，每个具有不同总线宽度的多条数据总线以及写入方式控制单元或地址控制单元，无论哪种能够切换这些高速缓冲存储器的路数或条目数单元，根据由指定的数据总线确定的总线模式和访问特定的高速缓冲存储器单元，其中通过根据设置的总线模式切换方式或条目的数量，所获取的指令和数据的字节数量完全一致在任何总线模式期间各个高速缓冲存储器单元的数据宽度（行大小）。这反过来完全消除了各个高速缓冲存储器单元的未使用区域，以提供使用整个高速缓冲存储器单元的改进的效率。

6. 发明授权

US4827444A Carry skip-ahead circuit for Manchester-type adder chain 失效
标题翻译：进行曼彻斯特型加法器链的跳过电路
公开(公告)号：US4827444A
公开(公告)日：1989-05-02
申请号：US884173
申请日：1986-07-09
申请人： Satoshi Akiyama , Yuuichi Saito
发明人： Satoshi Akiyama , Yuuichi Saito
IPC分类号： G06F7/50 , G06F7/506
CPC分类号： G06F7/506
摘要： A bypass circuit (20) opens transmission gates (13) through (16) when the condition is satisfied that two bit values Ai and Bi (i=0, 1, . . . n) to each full adder (1) are non-coincident with each other throughout the full adders. To this end, the inverse of the initial carry signal C.sub.0 is outputted as the addition results S.sub.0 and S.sub.n and the initial carry signal C.sub.0 is outputted as the final stage output signal C.sub.n.
摘要翻译：当条件满足每个全加器（1）的两个位值Ai和Bi（i = 0,1，...）为非零值时，旁路电路（20）打开传输门（13）至（16）在整个加法器中相互重合。为此，将初始进位信号C0的反相作为加法结果S0和Sn输出，并将初始进位信号C0作为最后级输出信号Cn输出。

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